| Huan Zhou | 3c23b93 | 2025-03-11 09:38:48 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright (C) 2022 Spacemit Inc. |
| 4 | * Copyright (C) 2025 Huan Zhou <pericycle.cc@gmail.com> |
| 5 | */ |
| 6 | |
| 7 | #ifndef __DT_BINDINGS_RESET_SAPCEMIT_K1_H__ |
| 8 | #define __DT_BINDINGS_RESET_SAPCEMIT_K1_H__ |
| 9 | /* APBC */ |
| 10 | #define RESET_UART1 1 |
| 11 | #define RESET_UART2 2 |
| 12 | #define RESET_GPIO 3 |
| 13 | #define RESET_PWM0 4 |
| 14 | #define RESET_PWM1 5 |
| 15 | #define RESET_PWM2 6 |
| 16 | #define RESET_PWM3 7 |
| 17 | #define RESET_PWM4 8 |
| 18 | #define RESET_PWM5 9 |
| 19 | #define RESET_PWM6 10 |
| 20 | #define RESET_PWM7 11 |
| 21 | #define RESET_PWM8 12 |
| 22 | #define RESET_PWM9 13 |
| 23 | #define RESET_PWM10 14 |
| 24 | #define RESET_PWM11 15 |
| 25 | #define RESET_PWM12 16 |
| 26 | #define RESET_PWM13 17 |
| 27 | #define RESET_PWM14 18 |
| 28 | #define RESET_PWM15 19 |
| 29 | #define RESET_PWM16 20 |
| 30 | #define RESET_PWM17 21 |
| 31 | #define RESET_PWM18 22 |
| 32 | #define RESET_PWM19 23 |
| 33 | #define RESET_SSP3 24 |
| 34 | #define RESET_UART3 25 |
| 35 | #define RESET_RTC 26 |
| 36 | #define RESET_TWSI0 27 |
| 37 | #define RESET_TIMERS1 28 |
| 38 | #define RESET_AIB 29 |
| 39 | #define RESET_TIMERS2 30 |
| 40 | #define RESET_ONEWIRE 31 |
| 41 | #define RESET_SSPA0 32 |
| 42 | #define RESET_SSPA1 33 |
| 43 | #define RESET_DRO 34 |
| 44 | #define RESET_IR 35 |
| 45 | #define RESET_TWSI1 36 |
| 46 | #define RESET_TSEN 37 |
| 47 | #define RESET_TWSI2 38 |
| 48 | #define RESET_TWSI4 39 |
| 49 | #define RESET_TWSI5 40 |
| 50 | #define RESET_TWSI6 41 |
| 51 | #define RESET_TWSI7 42 |
| 52 | #define RESET_TWSI8 43 |
| 53 | #define RESET_IPC_AP2AUD 44 |
| 54 | #define RESET_UART4 45 |
| 55 | #define RESET_UART5 46 |
| 56 | #define RESET_UART6 47 |
| 57 | #define RESET_UART7 48 |
| 58 | #define RESET_UART8 49 |
| 59 | #define RESET_UART9 50 |
| 60 | #define RESET_CAN0 51 |
| 61 | |
| 62 | /* MPMU */ |
| 63 | #define RESET_WDT 52 |
| 64 | |
| 65 | /* APMU */ |
| 66 | #define RESET_JPG 53 |
| 67 | #define RESET_CSI 54 |
| 68 | #define RESET_CCIC2_PHY 55 |
| 69 | #define RESET_CCIC3_PHY 56 |
| 70 | #define RESET_ISP 57 |
| 71 | #define RESET_ISP_AHB 58 |
| 72 | #define RESET_ISP_CI 59 |
| 73 | #define RESET_ISP_CPP 60 |
| 74 | #define RESET_LCD 61 |
| 75 | #define RESET_DSI_ESC 62 |
| 76 | #define RESET_V2D 63 |
| 77 | #define RESET_MIPI 64 |
| 78 | #define RESET_LCD_SPI 65 |
| 79 | #define RESET_LCD_SPI_BUS 66 |
| 80 | #define RESET_LCD_SPI_HBUS 67 |
| 81 | #define RESET_LCD_MCLK 68 |
| 82 | #define RESET_CCIC_4X 69 |
| 83 | #define RESET_CCIC1_PHY 70 |
| 84 | #define RESET_SDH_AXI 71 |
| 85 | #define RESET_SDH0 72 |
| 86 | #define RESET_SDH1 73 |
| 87 | #define RESET_USB_AXI 74 |
| 88 | #define RESET_USBP1_AXI 75 |
| 89 | #define RESET_USB3_0 76 |
| 90 | #define RESET_QSPI 77 |
| 91 | #define RESET_QSPI_BUS 78 |
| 92 | #define RESET_DMA 79 |
| 93 | #define RESET_AES 80 |
| 94 | #define RESET_VPU 81 |
| 95 | #define RESET_GPU 82 |
| 96 | #define RESET_SDH2 83 |
| 97 | #define RESET_MC 84 |
| 98 | #define RESET_EM_AXI 85 |
| 99 | #define RESET_EM 86 |
| 100 | #define RESET_AUDIO_SYS 87 |
| 101 | #define RESET_HDMI 88 |
| 102 | #define RESET_PCIE0 89 |
| 103 | #define RESET_PCIE1 90 |
| 104 | #define RESET_PCIE2 91 |
| 105 | #define RESET_EMAC0 92 |
| 106 | #define RESET_EMAC1 93 |
| 107 | |
| 108 | /* APBC2 */ |
| 109 | #define RESET_SEC_UART1 94 |
| 110 | #define RESET_SEC_SSP2 95 |
| 111 | #define RESET_SEC_TWSI3 96 |
| 112 | #define RESET_SEC_RTC 97 |
| 113 | #define RESET_SEC_TIMERS0 98 |
| 114 | #define RESET_SEC_KPC 99 |
| 115 | #define RESET_SEC_GPIO 100 |
| 116 | #define RESET_NUMBER 101 |
| 117 | |
| 118 | #endif |