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git01.mediatek.com / filogic / uboot / 0af9d01bcbdd8e995c102ff51ae7ba1be6a00fb1 / . / cpu / at91rm9200 / lowlevel.S
blob: 030f9e194a89626da111d9c4e95f71d221730df7 [file] [log] [blame]
wdenk70ae5b42004-10-10 17:05:18 +0000[diff] [blame]1/*
2 * Memory Setup stuff - taken from blob memsetup.S
3 *
4 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
wdenkcbb52882004-10-10 18:03:33 +0000[diff] [blame]5 * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
wdenk70ae5b42004-10-10 17:05:18 +0000[diff] [blame]6 *
7 * Modified for the at91rm9200dk board by
8 * (C) Copyright 2004
wdenk20dd2fa2004-11-21 00:06:33 +0000[diff] [blame]9 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
wdenk70ae5b42004-10-10 17:05:18 +0000[diff] [blame]10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenkcbb52882004-10-10 18:03:33 +0000[diff] [blame]21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenk70ae5b42004-10-10 17:05:18 +0000[diff] [blame]22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#include <config.h>
31#include <version.h>
32
33#ifdef CONFIG_BOOTBINFUNC
34/*
35 * some parameters for the board
36 *
37 * This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in
wdenk20dd2fa2004-11-21 00:06:33 +0000[diff] [blame]38 * turn is based on the boot.bin code from ATMEL
wdenk70ae5b42004-10-10 17:05:18 +0000[diff] [blame]39 *
40 */
41
42/* flash */
wdenk0af9d012005-03-31 23:44:33 +0000[diff] [blame^]43#define MC_PUIA 0xFFFFFF10
44#define MC_PUP 0xFFFFFF50
45#define MC_PUER 0xFFFFFF54
46#define MC_ASR 0xFFFFFF04
47#define MC_AASR 0xFFFFFF08
48#define EBI_CFGR 0xFFFFFF64
49#define SMC2_CSR 0xFFFFFF70
wdenk70ae5b42004-10-10 17:05:18 +0000[diff] [blame]50
51/* clocks */
wdenk0af9d012005-03-31 23:44:33 +0000[diff] [blame^]52#define PLLAR 0xFFFFFC28
53#define PLLBR 0xFFFFFC2C
54#define MCKR 0xFFFFFC30
55
56#define AT91C_BASE_CKGR 0xFFFFFC20
57#define CKGR_MOR 0
wdenk70ae5b42004-10-10 17:05:18 +0000[diff] [blame]58
59/* sdram */
wdenk0af9d012005-03-31 23:44:33 +0000[diff] [blame^]60#define PIOC_ASR 0xFFFFF870
61#define PIOC_BSR 0xFFFFF874
62#define PIOC_PDR 0xFFFFF804
63#define EBI_CSA 0xFFFFFF60
64#define SDRC_CR 0xFFFFFF98
65#define SDRC_MR 0xFFFFFF90
66#define SDRC_TR 0xFFFFFF94
wdenk70ae5b42004-10-10 17:05:18 +0000[diff] [blame]67
68
wdenk20dd2fa2004-11-21 00:06:33 +0000[diff] [blame]69_MTEXT_BASE:
70#undef START_FROM_MEM
71#ifdef START_FROM_MEM
72 .word TEXT_BASE-PHYS_FLASH_1
73#else
wdenk70ae5b42004-10-10 17:05:18 +0000[diff] [blame]74 .word TEXT_BASE
wdenk20dd2fa2004-11-21 00:06:33 +0000[diff] [blame]75#endif
wdenk70ae5b42004-10-10 17:05:18 +0000[diff] [blame]76
wdenk20dd2fa2004-11-21 00:06:33 +0000[diff] [blame]77.globl lowlevelinit
78lowlevelinit:
wdenk0af9d012005-03-31 23:44:33 +0000[diff] [blame^]79 /* Get the CKGR Base Address */
80 ldr r1, =AT91C_BASE_CKGR
81 /* Main oscillator Enable register */
82#ifdef CFG_USE_MAIN_OSCILLATOR
83 ldr r0, =0x0000FF01 /* Enable main oscillator, OSCOUNT = 0xFF */
84#else
85 ldr r0, =0x0000FF00 /* Disable main oscillator, OSCOUNT = 0xFF */
86#endif
87 str r0, [r1, #CKGR_MOR]
88 /* Add loop to compensate Main Oscillator startup time */
89 ldr r0, =0x00000010
90LoopOsc:
91 subs r0, r0, #1
92 bhi LoopOsc
93
wdenk70ae5b42004-10-10 17:05:18 +0000[diff] [blame]94 /* memory control configuration */
wdenkcbb52882004-10-10 18:03:33 +0000[diff] [blame]95 /* this isn't very elegant, but what the heck */
96 ldr r0, =SMRDATA
wdenk20dd2fa2004-11-21 00:06:33 +0000[diff] [blame]97 ldr r1, _MTEXT_BASE
wdenk70ae5b42004-10-10 17:05:18 +0000[diff] [blame]98 sub r0, r0, r1
wdenkcbb52882004-10-10 18:03:33 +0000[diff] [blame]99 add r2, r0, #80
wdenk70ae5b42004-10-10 17:05:18 +0000[diff] [blame]1000:
101 /* the address */
wdenkcbb52882004-10-10 18:03:33 +0000[diff] [blame]102 ldr r1, [r0], #4
wdenk70ae5b42004-10-10 17:05:18 +0000[diff] [blame]103 /* the value */
wdenkcbb52882004-10-10 18:03:33 +0000[diff] [blame]104 ldr r3, [r0], #4
105 str r3, [r1]
106 cmp r2, r0
107 bne 0b
wdenk70ae5b42004-10-10 17:05:18 +0000[diff] [blame]108 /* delay - this is all done by guess */
wdenk20dd2fa2004-11-21 00:06:33 +0000[diff] [blame]109 ldr r0, =0x00010000
wdenk70ae5b42004-10-10 17:05:18 +0000[diff] [blame]1101:
wdenkcbb52882004-10-10 18:03:33 +0000[diff] [blame]111 subs r0, r0, #1
112 bhi 1b
113 ldr r0, =SMRDATA1
wdenk20dd2fa2004-11-21 00:06:33 +0000[diff] [blame]114 ldr r1, _MTEXT_BASE
wdenk70ae5b42004-10-10 17:05:18 +0000[diff] [blame]115 sub r0, r0, r1
wdenkcbb52882004-10-10 18:03:33 +0000[diff] [blame]116 add r2, r0, #176
wdenk70ae5b42004-10-10 17:05:18 +0000[diff] [blame]1172:
118 /* the address */
wdenkcbb52882004-10-10 18:03:33 +0000[diff] [blame]119 ldr r1, [r0], #4
wdenk70ae5b42004-10-10 17:05:18 +0000[diff] [blame]120 /* the value */
wdenkcbb52882004-10-10 18:03:33 +0000[diff] [blame]121 ldr r3, [r0], #4
122 str r3, [r1]
123 cmp r2, r0
124 bne 2b
wdenk70ae5b42004-10-10 17:05:18 +0000[diff] [blame]125
126 /* everything is fine now */
127 mov pc, lr
128
129 .ltorg
130
131SMRDATA:
132 .word MC_PUIA
133 .word MC_PUIA_VAL
134 .word MC_PUP
135 .word MC_PUP_VAL
136 .word MC_PUER
137 .word MC_PUER_VAL
138 .word MC_ASR
139 .word MC_ASR_VAL
140 .word MC_AASR
141 .word MC_AASR_VAL
142 .word EBI_CFGR
143 .word EBI_CFGR_VAL
144 .word SMC2_CSR
145 .word SMC2_CSR_VAL
146 .word PLLAR
147 .word PLLAR_VAL
148 .word PLLBR
149 .word PLLBR_VAL
150 .word MCKR
151 .word MCKR_VAL
152 /* SMRDATA is 80 bytes long */
153 /* here there's a delay of 100 */
154SMRDATA1:
155 .word PIOC_ASR
156 .word PIOC_ASR_VAL
157 .word PIOC_BSR
158 .word PIOC_BSR_VAL
159 .word PIOC_PDR
160 .word PIOC_PDR_VAL
161 .word EBI_CSA
162 .word EBI_CSA_VAL
163 .word SDRC_CR
164 .word SDRC_CR_VAL
165 .word SDRC_MR
166 .word SDRC_MR_VAL
167 .word SDRAM
168 .word SDRAM_VAL
169 .word SDRC_MR
170 .word SDRC_MR_VAL1
171 .word SDRAM
172 .word SDRAM_VAL
173 .word SDRAM
174 .word SDRAM_VAL
175 .word SDRAM
176 .word SDRAM_VAL
177 .word SDRAM
178 .word SDRAM_VAL
179 .word SDRAM
180 .word SDRAM_VAL
181 .word SDRAM
182 .word SDRAM_VAL
183 .word SDRAM
184 .word SDRAM_VAL
185 .word SDRAM
186 .word SDRAM_VAL
187 .word SDRC_MR
188 .word SDRC_MR_VAL2
189 .word SDRAM1
190 .word SDRAM_VAL
191 .word SDRC_TR
192 .word SDRC_TR_VAL
193 .word SDRAM
194 .word SDRAM_VAL
195 .word SDRC_MR
196 .word SDRC_MR_VAL3
197 .word SDRAM
198 .word SDRAM_VAL
199 /* SMRDATA1 is 176 bytes long */
200#endif /* CONFIG_BOOTBINFUNC */