blob: a1c9eb3f468b9935cae10bdd90c18b50ca5699cd [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Ashish Kumar227b4bc2017-08-31 16:12:54 +05302/*
Pramod Kumara0531822018-10-12 14:04:27 +00003 * Copyright 2017-2018 NXP
Ashish Kumar227b4bc2017-08-31 16:12:54 +05304 */
5#include <common.h>
Simon Glass0af6e2d2019-08-01 09:46:52 -06006#include <env.h>
Ashish Kumar227b4bc2017-08-31 16:12:54 +05307#include <i2c.h>
8#include <malloc.h>
9#include <errno.h>
10#include <netdev.h>
11#include <fsl_ifc.h>
12#include <fsl_ddr.h>
13#include <fsl_sec.h>
14#include <asm/io.h>
15#include <fdt_support.h>
Masahiro Yamada75f82d02018-03-05 01:20:11 +090016#include <linux/libfdt.h>
Ashish Kumar227b4bc2017-08-31 16:12:54 +053017#include <fsl-mc/fsl_mc.h>
18#include <environment.h>
19#include <asm/arch-fsl-layerscape/soc.h>
20#include <asm/arch/ppa.h>
Yangbo Lu1d879532017-11-27 15:40:17 +080021#include <hwconfig.h>
Rajesh Bhagata4216252018-01-17 16:13:09 +053022#include <asm/arch/fsl_serdes.h>
23#include <asm/arch/soc.h>
Ashish Kumar227b4bc2017-08-31 16:12:54 +053024
25#include "../common/qixis.h"
26#include "ls1088a_qixis.h"
Rajesh Bhagata4216252018-01-17 16:13:09 +053027#include "../common/vid.h"
28#include <fsl_immap.h>
Ashish Kumar227b4bc2017-08-31 16:12:54 +053029
30DECLARE_GLOBAL_DATA_PTR;
31
Pankit Garg112aeba2018-12-27 04:37:57 +000032#ifdef CONFIG_TARGET_LS1088AQDS
33#ifdef CONFIG_TFABOOT
34struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
35 {
36 "nor0",
37 CONFIG_SYS_NOR0_CSPR_EARLY,
38 CONFIG_SYS_NOR0_CSPR_EXT,
39 CONFIG_SYS_NOR_AMASK,
40 CONFIG_SYS_NOR_CSOR,
41 {
42 CONFIG_SYS_NOR_FTIM0,
43 CONFIG_SYS_NOR_FTIM1,
44 CONFIG_SYS_NOR_FTIM2,
45 CONFIG_SYS_NOR_FTIM3
46 },
47 0,
48 CONFIG_SYS_NOR0_CSPR,
49 0,
50 },
51 {
52 "nor1",
53 CONFIG_SYS_NOR1_CSPR_EARLY,
54 CONFIG_SYS_NOR0_CSPR_EXT,
55 CONFIG_SYS_NOR_AMASK_EARLY,
56 CONFIG_SYS_NOR_CSOR,
57 {
58 CONFIG_SYS_NOR_FTIM0,
59 CONFIG_SYS_NOR_FTIM1,
60 CONFIG_SYS_NOR_FTIM2,
61 CONFIG_SYS_NOR_FTIM3
62 },
63 0,
64 CONFIG_SYS_NOR1_CSPR,
65 CONFIG_SYS_NOR_AMASK,
66 },
67 {
68 "nand",
69 CONFIG_SYS_NAND_CSPR,
70 CONFIG_SYS_NAND_CSPR_EXT,
71 CONFIG_SYS_NAND_AMASK,
72 CONFIG_SYS_NAND_CSOR,
73 {
74 CONFIG_SYS_NAND_FTIM0,
75 CONFIG_SYS_NAND_FTIM1,
76 CONFIG_SYS_NAND_FTIM2,
77 CONFIG_SYS_NAND_FTIM3
78 },
79 },
80 {
81 "fpga",
82 CONFIG_SYS_FPGA_CSPR,
83 CONFIG_SYS_FPGA_CSPR_EXT,
84 SYS_FPGA_AMASK,
85 CONFIG_SYS_FPGA_CSOR,
86 {
87 SYS_FPGA_CS_FTIM0,
88 SYS_FPGA_CS_FTIM1,
89 SYS_FPGA_CS_FTIM2,
90 SYS_FPGA_CS_FTIM3
91 },
92 0,
93 SYS_FPGA_CSPR_FINAL,
94 0,
95 }
96};
97
98struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
99 {
100 "nand",
101 CONFIG_SYS_NAND_CSPR,
102 CONFIG_SYS_NAND_CSPR_EXT,
103 CONFIG_SYS_NAND_AMASK,
104 CONFIG_SYS_NAND_CSOR,
105 {
106 CONFIG_SYS_NAND_FTIM0,
107 CONFIG_SYS_NAND_FTIM1,
108 CONFIG_SYS_NAND_FTIM2,
109 CONFIG_SYS_NAND_FTIM3
110 },
111 },
112 {
113 "reserved",
114 },
115 {
116 "fpga",
117 CONFIG_SYS_FPGA_CSPR,
118 CONFIG_SYS_FPGA_CSPR_EXT,
119 SYS_FPGA_AMASK,
120 CONFIG_SYS_FPGA_CSOR,
121 {
122 SYS_FPGA_CS_FTIM0,
123 SYS_FPGA_CS_FTIM1,
124 SYS_FPGA_CS_FTIM2,
125 SYS_FPGA_CS_FTIM3
126 },
127 0,
128 SYS_FPGA_CSPR_FINAL,
129 0,
130 }
131};
132
133void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
134{
135 enum boot_src src = get_boot_src();
136
137 if (src == BOOT_SOURCE_QSPI_NOR)
138 regs_info->regs = ifc_cfg_qspi_nor_boot;
139 else
140 regs_info->regs = ifc_cfg_ifc_nor_boot;
141
142 regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
143}
144#endif /* CONFIG_TFABOOT */
145#endif /* CONFIG_TARGET_LS1088AQDS */
146
Sumit Garg08da8b22018-01-06 09:04:24 +0530147int board_early_init_f(void)
148{
Ashish Kumarf719b192018-02-19 14:14:53 +0530149#if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS)
150 i2c_early_init_f();
151#endif
Sumit Garg08da8b22018-01-06 09:04:24 +0530152 fsl_lsch3_early_init_f();
153 return 0;
154}
155
156#ifdef CONFIG_FSL_QIXIS
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530157unsigned long long get_qixis_addr(void)
158{
159 unsigned long long addr;
160
161 if (gd->flags & GD_FLG_RELOC)
162 addr = QIXIS_BASE_PHYS;
163 else
164 addr = QIXIS_BASE_PHYS_EARLY;
165
166 /*
167 * IFC address under 256MB is mapped to 0x30000000, any address above
168 * is mapped to 0x5_10000000 up to 4GB.
169 */
170 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
171
172 return addr;
173}
Sumit Garg08da8b22018-01-06 09:04:24 +0530174#endif
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530175
Rajesh Bhagata4216252018-01-17 16:13:09 +0530176#if defined(CONFIG_VID)
177int init_func_vid(void)
178{
179 if (adjust_vdd(0) < 0)
180 printf("core voltage not adjusted\n");
181
182 return 0;
183}
184#endif
185
Pramod Kumara0531822018-10-12 14:04:27 +0000186int is_pb_board(void)
187{
188 u8 board_id;
189
190 board_id = QIXIS_READ(id);
191 if (board_id == LS1088ARDB_PB_BOARD)
192 return 1;
193 else
194 return 0;
195}
196
197int fixup_ls1088ardb_pb_banner(void *fdt)
198{
199 fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board");
200
201 return 0;
202}
203
Sumit Garg08da8b22018-01-06 09:04:24 +0530204#if !defined(CONFIG_SPL_BUILD)
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530205int checkboard(void)
206{
Pankit Gargf5c2a832018-12-27 04:37:55 +0000207#ifdef CONFIG_TFABOOT
208 enum boot_src src = get_boot_src();
209#endif
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530210 char buf[64];
211 u8 sw;
212 static const char *const freq[] = {"100", "125", "156.25",
213 "100 separate SSCG"};
214 int clock;
215
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530216#ifdef CONFIG_TARGET_LS1088AQDS
217 printf("Board: LS1088A-QDS, ");
218#else
Pramod Kumara0531822018-10-12 14:04:27 +0000219 if (is_pb_board())
220 printf("Board: LS1088ARDB-PB, ");
221 else
222 printf("Board: LS1088A-RDB, ");
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530223#endif
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530224
225 sw = QIXIS_READ(arch);
226 printf("Board Arch: V%d, ", sw >> 4);
227
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530228#ifdef CONFIG_TARGET_LS1088AQDS
229 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
230#else
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530231 printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530232#endif
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530233
234 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
235
236 sw = QIXIS_READ(brdcfg[0]);
237 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
238
Pankit Gargf5c2a832018-12-27 04:37:55 +0000239#ifdef CONFIG_TFABOOT
240 if (src == BOOT_SOURCE_SD_MMC)
241 puts("SD card\n");
242#else
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530243#ifdef CONFIG_SD_BOOT
244 puts("SD card\n");
245#endif
Pankit Gargf5c2a832018-12-27 04:37:55 +0000246#endif /* CONFIG_TFABOOT */
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530247 switch (sw) {
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530248#ifdef CONFIG_TARGET_LS1088AQDS
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530249 case 0:
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530250 case 1:
251 case 2:
252 case 3:
253 case 4:
254 case 5:
255 case 6:
256 case 7:
257 printf("vBank: %d\n", sw);
258 break;
259 case 8:
260 puts("PromJet\n");
261 break;
262 case 15:
263 puts("IFCCard\n");
264 break;
265 case 14:
266#else
267 case 0:
268#endif
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530269 puts("QSPI:");
270 sw = QIXIS_READ(brdcfg[0]);
271 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
272 if (sw == 0 || sw == 4)
273 puts("0\n");
274 else if (sw == 1)
275 puts("1\n");
276 else
277 puts("EMU\n");
278 break;
279
280 default:
281 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
282 break;
283 }
284
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530285#ifdef CONFIG_TARGET_LS1088AQDS
286 printf("FPGA: v%d (%s), build %d",
287 (int)QIXIS_READ(scver), qixis_read_tag(buf),
288 (int)qixis_read_minor());
289 /* the timestamp string contains "\n" at the end */
290 printf(" on %s", qixis_read_time(buf));
291#else
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530292 printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530293#endif
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530294
295 /*
296 * Display the actual SERDES reference clocks as configured by the
297 * dip switches on the board. Note that the SWx registers could
298 * technically be set to force the reference clocks to match the
299 * values that the SERDES expects (or vice versa). For now, however,
300 * we just display both values and hope the user notices when they
301 * don't match.
302 */
303 puts("SERDES1 Reference : ");
304 sw = QIXIS_READ(brdcfg[2]);
305 clock = (sw >> 6) & 3;
306 printf("Clock1 = %sMHz ", freq[clock]);
307 clock = (sw >> 4) & 3;
308 printf("Clock2 = %sMHz", freq[clock]);
309
310 puts("\nSERDES2 Reference : ");
311 clock = (sw >> 2) & 3;
312 printf("Clock1 = %sMHz ", freq[clock]);
313 clock = (sw >> 0) & 3;
314 printf("Clock2 = %sMHz\n", freq[clock]);
315
316 return 0;
317}
Ashish Kumard029b272018-02-19 14:14:52 +0530318#endif
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530319
320bool if_board_diff_clk(void)
321{
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530322#ifdef CONFIG_TARGET_LS1088AQDS
323 u8 diff_conf = QIXIS_READ(brdcfg[11]);
324 return diff_conf & 0x40;
325#else
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530326 u8 diff_conf = QIXIS_READ(dutcfg[11]);
327 return diff_conf & 0x80;
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530328#endif
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530329}
330
331unsigned long get_board_sys_clk(void)
332{
333 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
334
335 switch (sysclk_conf & 0x0f) {
336 case QIXIS_SYSCLK_83:
337 return 83333333;
338 case QIXIS_SYSCLK_100:
339 return 100000000;
340 case QIXIS_SYSCLK_125:
341 return 125000000;
342 case QIXIS_SYSCLK_133:
343 return 133333333;
344 case QIXIS_SYSCLK_150:
345 return 150000000;
346 case QIXIS_SYSCLK_160:
347 return 160000000;
348 case QIXIS_SYSCLK_166:
349 return 166666666;
350 }
351
352 return 66666666;
353}
354
355unsigned long get_board_ddr_clk(void)
356{
357 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
358
359 if (if_board_diff_clk())
360 return get_board_sys_clk();
361 switch ((ddrclk_conf & 0x30) >> 4) {
362 case QIXIS_DDRCLK_100:
363 return 100000000;
364 case QIXIS_DDRCLK_125:
365 return 125000000;
366 case QIXIS_DDRCLK_133:
367 return 133333333;
368 }
369
370 return 66666666;
371}
372
373int select_i2c_ch_pca9547(u8 ch)
374{
375 int ret;
376
377 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
378 if (ret) {
379 puts("PCA: failed to select proper channel\n");
380 return ret;
381 }
382
383 return 0;
384}
385
Rajesh Bhagat6d809b82018-01-17 16:13:10 +0530386#if !defined(CONFIG_SPL_BUILD)
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530387void board_retimer_init(void)
388{
389 u8 reg;
390
391 /* Retimer is connected to I2C1_CH5 */
392 select_i2c_ch_pca9547(I2C_MUX_CH5);
393
394 /* Access to Control/Shared register */
395 reg = 0x0;
396 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
397
398 /* Read device revision and ID */
399 i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
400 debug("Retimer version id = 0x%x\n", reg);
401
402 /* Enable Broadcast. All writes target all channel register sets */
403 reg = 0x0c;
404 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
405
406 /* Reset Channel Registers */
407 i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
408 reg |= 0x4;
409 i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
410
411 /* Set data rate as 10.3125 Gbps */
412 reg = 0x90;
413 i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
414 reg = 0xb3;
415 i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
416 reg = 0x90;
417 i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
418 reg = 0xb3;
419 i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
420 reg = 0xcd;
421 i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
422
423 /* Select VCO Divider to full rate (000) */
424 i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
425 reg &= 0x0f;
426 reg |= 0x70;
427 i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
428
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530429#ifdef CONFIG_TARGET_LS1088AQDS
430 /* Retimer is connected to I2C1_CH5 */
431 select_i2c_ch_pca9547(I2C_MUX_CH5);
432
433 /* Access to Control/Shared register */
434 reg = 0x0;
435 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530436
Ashish Kumar1ef4c772017-08-31 16:12:55 +0530437 /* Read device revision and ID */
438 i2c_read(I2C_RETIMER_ADDR2, 1, 1, &reg, 1);
439 debug("Retimer version id = 0x%x\n", reg);
440
441 /* Enable Broadcast. All writes target all channel register sets */
442 reg = 0x0c;
443 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
444
445 /* Reset Channel Registers */
446 i2c_read(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
447 reg |= 0x4;
448 i2c_write(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
449
450 /* Set data rate as 10.3125 Gbps */
451 reg = 0x90;
452 i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, &reg, 1);
453 reg = 0xb3;
454 i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, &reg, 1);
455 reg = 0x90;
456 i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, &reg, 1);
457 reg = 0xb3;
458 i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, &reg, 1);
459 reg = 0xcd;
460 i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, &reg, 1);
461
462 /* Select VCO Divider to full rate (000) */
463 i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
464 reg &= 0x0f;
465 reg |= 0x70;
466 i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
467#endif
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530468 /*return the default channel*/
469 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
470}
471
Yangbo Lu1d879532017-11-27 15:40:17 +0800472#ifdef CONFIG_MISC_INIT_R
473int misc_init_r(void)
474{
475#ifdef CONFIG_TARGET_LS1088ARDB
476 u8 brdcfg5;
477
478 if (hwconfig("esdhc-force-sd")) {
479 brdcfg5 = QIXIS_READ(brdcfg[5]);
480 brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
481 brdcfg5 |= BRDCFG5_FORCE_SD;
482 QIXIS_WRITE(brdcfg[5], brdcfg5);
483 }
484#endif
485 return 0;
486}
487#endif
Rajesh Bhagat6d809b82018-01-17 16:13:10 +0530488#endif
Yangbo Lu1d879532017-11-27 15:40:17 +0800489
Rajesh Bhagata4216252018-01-17 16:13:09 +0530490int i2c_multiplexer_select_vid_channel(u8 channel)
491{
492 return select_i2c_ch_pca9547(channel);
493}
494
495#ifdef CONFIG_TARGET_LS1088AQDS
496/* read the current value(SVDD) of the LTM Regulator Voltage */
497int get_serdes_volt(void)
498{
499 int ret, vcode = 0;
500 u8 chan = PWM_CHANNEL0;
501
502 /* Select the PAGE 0 using PMBus commands PAGE for VDD */
503 ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
504 PMBUS_CMD_PAGE, 1, &chan, 1);
505 if (ret) {
506 printf("VID: failed to select VDD Page 0\n");
507 return ret;
508 }
509
510 /* Read the output voltage using PMBus command READ_VOUT */
511 ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
512 PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
513 if (ret) {
514 printf("VID: failed to read the volatge\n");
515 return ret;
516 }
517
518 return vcode;
519}
520
521int set_serdes_volt(int svdd)
522{
523 int ret, vdd_last;
524 u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
525 svdd & 0xFF, (svdd & 0xFF00) >> 8};
526
527 /* Write the desired voltage code to the SVDD regulator */
528 ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
529 PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
530 if (ret) {
531 printf("VID: I2C failed to write to the volatge regulator\n");
532 return -1;
533 }
534
535 /* Wait for the volatge to get to the desired value */
536 do {
537 vdd_last = get_serdes_volt();
538 if (vdd_last < 0) {
539 printf("VID: Couldn't read sensor abort VID adjust\n");
540 return -1;
541 }
542 } while (vdd_last != svdd);
543
544 return 1;
545}
546#else
547int get_serdes_volt(void)
548{
549 return 0;
550}
551
552int set_serdes_volt(int svdd)
553{
554 int ret;
555 u8 brdcfg4;
556
557 printf("SVDD changing of RDB\n");
558
559 /* Read the BRDCFG54 via CLPD */
560 ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
561 QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
562 if (ret) {
563 printf("VID: I2C failed to read the CPLD BRDCFG4\n");
564 return -1;
565 }
566
567 brdcfg4 = brdcfg4 | 0x08;
568
569 /* Write to the BRDCFG4 */
570 ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
571 QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
572 if (ret) {
573 debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
574 return -1;
575 }
576
577 /* Wait for the volatge to get to the desired value */
578 udelay(10000);
579
580 return 1;
581}
582#endif
583
584/* this function disables the SERDES, changes the SVDD Voltage and enables it*/
585int board_adjust_vdd(int vdd)
586{
587 int ret = 0;
588
589 debug("%s: vdd = %d\n", __func__, vdd);
590
591 /* Special settings to be performed when voltage is 900mV */
592 if (vdd == 900) {
593 ret = setup_serdes_volt(vdd);
594 if (ret < 0) {
595 ret = -1;
596 goto exit;
597 }
598 }
599exit:
600 return ret;
601}
602
Rajesh Bhagat6d809b82018-01-17 16:13:10 +0530603#if !defined(CONFIG_SPL_BUILD)
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530604int board_init(void)
605{
606 init_final_memctl_regs();
607#if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
608 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
609#endif
610
611 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
612 board_retimer_init();
613
614#ifdef CONFIG_ENV_IS_NOWHERE
615 gd->env_addr = (ulong)&default_environment[0];
616#endif
617
618#if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
619 /* invert AQR105 IRQ pins polarity */
620 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
621#endif
622
Udit Agarwal09fd5792017-11-22 09:01:26 +0530623#ifdef CONFIG_FSL_CAAM
624 sec_init();
625#endif
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530626#ifdef CONFIG_FSL_LS_PPA
627 ppa_init();
628#endif
629 return 0;
630}
631
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530632void detail_board_ddr_info(void)
633{
634 puts("\nDDR ");
635 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
636 print_ddr_info(0);
637}
638
639#if defined(CONFIG_ARCH_MISC_INIT)
640int arch_misc_init(void)
641{
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530642 return 0;
643}
644#endif
645
646#ifdef CONFIG_FSL_MC_ENET
Mian Yousaf Kaukabe1dabf02019-01-29 16:38:30 +0100647void board_quiesce_devices(void)
648{
649 fsl_mc_ldpaa_exit(gd->bd);
650}
651
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530652void fdt_fixup_board_enet(void *fdt)
653{
654 int offset;
655
656 offset = fdt_path_offset(fdt, "/fsl-mc");
657
658 if (offset < 0)
Mian Yousaf Kaukab775c0912019-01-29 16:38:31 +0100659 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530660
661 if (offset < 0) {
662 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
663 __func__, offset);
664 return;
665 }
666
Mian Yousaf Kaukab97124652018-12-18 14:01:17 +0100667 if (get_mc_boot_status() == 0 &&
668 (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530669 fdt_status_okay(fdt, offset);
670 else
671 fdt_status_fail(fdt, offset);
672}
673#endif
674
675#ifdef CONFIG_OF_BOARD_SETUP
Ashish Kumarff12b8a2017-11-09 11:14:24 +0530676void fsl_fdt_fixup_flash(void *fdt)
677{
678 int offset;
Pankit Gargf5c2a832018-12-27 04:37:55 +0000679#ifdef CONFIG_TFABOOT
680 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
681 u32 val;
682#endif
Ashish Kumarff12b8a2017-11-09 11:14:24 +0530683
684/*
685 * IFC-NOR and QSPI are muxed on SoC.
686 * So disable IFC node in dts if QSPI is enabled or
687 * disable QSPI node in dts in case QSPI is not enabled.
688 */
689
Pankit Gargf5c2a832018-12-27 04:37:55 +0000690#ifdef CONFIG_TFABOOT
691 enum boot_src src = get_boot_src();
692 bool disable_ifc = false;
693
694 switch (src) {
695 case BOOT_SOURCE_IFC_NOR:
696 disable_ifc = false;
697 break;
698 case BOOT_SOURCE_QSPI_NOR:
699 disable_ifc = true;
700 break;
701 default:
702 val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
703 if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
704 disable_ifc = true;
705 break;
706 }
707
708 if (disable_ifc) {
709 offset = fdt_path_offset(fdt, "/soc/ifc/nor");
710
711 if (offset < 0)
712 offset = fdt_path_offset(fdt, "/ifc/nor");
713 } else {
714 offset = fdt_path_offset(fdt, "/soc/quadspi");
715
716 if (offset < 0)
717 offset = fdt_path_offset(fdt, "/quadspi");
718 }
719
720#else
Ashish Kumarff12b8a2017-11-09 11:14:24 +0530721#ifdef CONFIG_FSL_QSPI
722 offset = fdt_path_offset(fdt, "/soc/ifc/nor");
723
724 if (offset < 0)
725 offset = fdt_path_offset(fdt, "/ifc/nor");
726#else
727 offset = fdt_path_offset(fdt, "/soc/quadspi");
728
729 if (offset < 0)
730 offset = fdt_path_offset(fdt, "/quadspi");
731#endif
Pankit Gargf5c2a832018-12-27 04:37:55 +0000732#endif
Ashish Kumarff12b8a2017-11-09 11:14:24 +0530733 if (offset < 0)
734 return;
735
736 fdt_status_disabled(fdt, offset);
737}
738
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530739int ft_board_setup(void *blob, bd_t *bd)
740{
Mian Yousaf Kaukabe1dabf02019-01-29 16:38:30 +0100741 int i;
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530742 u64 base[CONFIG_NR_DRAM_BANKS];
743 u64 size[CONFIG_NR_DRAM_BANKS];
744
745 ft_cpu_setup(blob, bd);
746
747 /* fixup DT for the two GPP DDR banks */
748 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
749 base[i] = gd->bd->bi_dram[i].start;
750 size[i] = gd->bd->bi_dram[i].size;
751 }
752
753#ifdef CONFIG_RESV_RAM
754 /* reduce size if reserved memory is within this bank */
755 if (gd->arch.resv_ram >= base[0] &&
756 gd->arch.resv_ram < base[0] + size[0])
757 size[0] = gd->arch.resv_ram - base[0];
758 else if (gd->arch.resv_ram >= base[1] &&
759 gd->arch.resv_ram < base[1] + size[1])
760 size[1] = gd->arch.resv_ram - base[1];
761#endif
762
763 fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
764
Nipun Guptad6912642018-08-20 16:01:14 +0530765 fdt_fsl_mc_fixup_iommu_map_entry(blob);
766
Ashish Kumarff12b8a2017-11-09 11:14:24 +0530767 fsl_fdt_fixup_flash(blob);
768
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530769#ifdef CONFIG_FSL_MC_ENET
770 fdt_fixup_board_enet(blob);
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530771#endif
Pramod Kumara0531822018-10-12 14:04:27 +0000772 if (is_pb_board())
773 fixup_ls1088ardb_pb_banner(blob);
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530774
775 return 0;
776}
777#endif
Sumit Garg08da8b22018-01-06 09:04:24 +0530778#endif /* defined(CONFIG_SPL_BUILD) */
Pankit Gargf5c2a832018-12-27 04:37:55 +0000779
780#ifdef CONFIG_TFABOOT
781#ifdef CONFIG_MTD_NOR_FLASH
782int is_flash_available(void)
783{
784 char *env_hwconfig = env_get("hwconfig");
785 enum boot_src src = get_boot_src();
786 int is_nor_flash_available = 1;
787
788 switch (src) {
789 case BOOT_SOURCE_IFC_NOR:
790 is_nor_flash_available = 1;
791 break;
792 case BOOT_SOURCE_QSPI_NOR:
793 is_nor_flash_available = 0;
794 break;
795 /*
796 * In Case of SD boot,if qspi is defined in env_hwconfig
797 * disable nor flash probe.
798 */
799 default:
800 if (hwconfig_f("qspi", env_hwconfig))
801 is_nor_flash_available = 0;
802 break;
803 }
804 return is_nor_flash_available;
805}
806#endif
807
808void *env_sf_get_env_addr(void)
809{
810 return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
811}
812#endif