Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Graeme Russ | a875dda | 2011-12-23 16:51:29 +1100 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2011 |
| 4 | * Graeme Russ, <graeme.russ@gmail.com> |
Graeme Russ | a875dda | 2011-12-23 16:51:29 +1100 | [diff] [blame] | 5 | */ |
Bin Meng | 535109a | 2015-08-13 00:29:10 -0700 | [diff] [blame] | 6 | |
Graeme Russ | a875dda | 2011-12-23 16:51:29 +1100 | [diff] [blame] | 7 | #include <common.h> |
Masahiro Yamada | 56a931c | 2016-09-21 11:28:55 +0900 | [diff] [blame] | 8 | #include <linux/errno.h> |
Simon Glass | 004ba17 | 2015-01-01 16:18:11 -0700 | [diff] [blame] | 9 | #include <asm/mtrr.h> |
Graeme Russ | a875dda | 2011-12-23 16:51:29 +1100 | [diff] [blame] | 10 | |
| 11 | DECLARE_GLOBAL_DATA_PTR; |
| 12 | |
Simon Glass | 3297d4d | 2013-02-28 19:26:10 +0000 | [diff] [blame] | 13 | /* Get the top of usable RAM */ |
| 14 | __weak ulong board_get_usable_ram_top(ulong total_size) |
Graeme Russ | 3fb4f9e | 2011-12-23 21:14:22 +1100 | [diff] [blame] | 15 | { |
Simon Glass | 3297d4d | 2013-02-28 19:26:10 +0000 | [diff] [blame] | 16 | return gd->ram_size; |
| 17 | } |
| 18 | |
Graeme Russ | 3fb4f9e | 2011-12-23 21:14:22 +1100 | [diff] [blame] | 19 | int init_cache_f_r(void) |
| 20 | { |
Park, Aiden | 5195143 | 2019-08-03 08:31:20 +0000 | [diff] [blame] | 21 | #if CONFIG_IS_ENABLED(X86_32BIT_INIT) && !defined(CONFIG_HAVE_FSP) && \ |
| 22 | !defined(CONFIG_SYS_SLIMBOOTLOADER) |
Simon Glass | 004ba17 | 2015-01-01 16:18:11 -0700 | [diff] [blame] | 23 | int ret; |
| 24 | |
| 25 | ret = mtrr_commit(false); |
Bin Meng | 80d2976 | 2015-01-22 11:29:41 +0800 | [diff] [blame] | 26 | /* If MTRR MSR is not implemented by the processor, just ignore it */ |
| 27 | if (ret && ret != -ENOSYS) |
Simon Glass | 004ba17 | 2015-01-01 16:18:11 -0700 | [diff] [blame] | 28 | return ret; |
| 29 | #endif |
Graeme Russ | 3fb4f9e | 2011-12-23 21:14:22 +1100 | [diff] [blame] | 30 | /* Initialise the CPU cache(s) */ |
| 31 | return init_cache(); |
| 32 | } |