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git01.mediatek.com / filogic / uboot / 0ae0760ab322836d72fff12daa1491a8bbbd2f4d / . / include / configs / ethernut5.h
blob: 807c6963192f10aefb3ba4fe5a16bcbf6b6dc38d [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]2/*
3 * (C) Copyright 2011
4 * egnite GmbH <info@egnite.de>
5 *
6 * Configuation settings for Ethernut 5 with AT91SAM9XE.
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]7 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12#include <asm/hardware.h>
13
14/* The first stage boot loader expects u-boot running at this address. */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]15
16/* The first stage boot loader takes care of low level initialization. */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]17
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]18/* CPU information */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]19
20/* ARM asynchronous clock */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]21#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
22#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]23
24/* 32kB internal SRAM */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]25#define CFG_SYS_INIT_RAM_ADDR 0x00300000 /*AT91SAM9XE_SRAM_BASE */
26#define CFG_SYS_INIT_RAM_SIZE (32 << 10)
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]27
28/* 128MB SDRAM in 1 bank */
Tom Rinibb4dd962022-11-16 13:10:37 -0500[diff] [blame]29#define CFG_SYS_SDRAM_BASE 0x20000000
30#define CFG_SYS_SDRAM_SIZE (128 << 20)
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]31
32/* 512kB on-chip NOR flash */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]33# define CFG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]34
Wenyou.Yang@microchip.comc99bfb42017-07-21 14:30:57 +0800[diff] [blame]35/* bootstrap + u-boot + env + linux in dataflash on CS0 */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]36
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]37/* NAND flash */
38#ifdef CONFIG_CMD_NAND
Tom Rinib4213492022-11-12 17:36:51 -0500[diff] [blame]39#define CFG_SYS_NAND_BASE 0x40000000
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]40/* our ALE is AD21 */
Tom Rinib4213492022-11-12 17:36:51 -0500[diff] [blame]41#define CFG_SYS_NAND_MASK_ALE (1 << 21)
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]42/* our CLE is AD22 */
Tom Rinib4213492022-11-12 17:36:51 -0500[diff] [blame]43#define CFG_SYS_NAND_MASK_CLE (1 << 22)
44#define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]45#endif
46
47/* JFFS2 */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]48
49/* Ethernet */
Tom Rinicd1b17e2022-12-04 10:13:28 -0500[diff] [blame]50#define CFG_PHY_ID 0
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]51
52/* MMC */
53#ifdef CONFIG_CMD_MMC
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]54#define CFG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]55#endif
56
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]57/* RTC */
58#if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]59#define CFG_SYS_I2C_RTC_ADDR 0x51
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]60#endif
61
62/* I2C */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]63#define CFG_SYS_MAX_I2C_BUS 1
Heiko Schocher479a4cf2013-01-29 08:53:15 +0100[diff] [blame]64
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]65#define I2C_SOFT_DECLARATIONS
66
67#define GPIO_I2C_SCL AT91_PIO_PORTA, 24
68#define GPIO_I2C_SDA AT91_PIO_PORTA, 23
69
70#define I2C_INIT { \
71 at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \
72 at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
73 at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \
74 at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \
75 at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
76}
77
78#define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0)
79#define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0)
80#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
81#define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit)
82#define I2C_DELAY udelay(100)
83#define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23)
84
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]85/* File systems */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]86
87/* Boot command */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]88
89/* Misc. u-boot settings */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]90
91#endif