blob: 07a367c3ad158b0285576c6646519e058fcc0c13 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Vladimir Zapolskiy89f86a22015-07-18 01:47:11 +03002/*
3 * Timll DevKit3250 board support, SPL board configuration
4 *
5 * (C) Copyright 2015 Vladimir Zapolskiy <vz@mleia.com>
Vladimir Zapolskiy89f86a22015-07-18 01:47:11 +03006 */
7
Vladimir Zapolskiy89f86a22015-07-18 01:47:11 +03008#include <asm/io.h>
9#include <asm/arch/sys_proto.h>
10#include <asm/arch/cpu.h>
11#include <asm/arch/emc.h>
12#include <asm/arch-lpc32xx/gpio.h>
13#include <spl.h>
14
15static struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
16
17/*
18 * SDRAM K4S561632N-LC60 settings are selected in assumption that
19 * SDRAM clock may be set up to 166 MHz, however at the moment
20 * it is 104 MHz. Most delay values are converted to be a multiple of
21 * base clock, and precise pinned values are not needed here.
22 */
23struct emc_dram_settings dram_64mb = {
24 .cmddelay = 0x0001C000,
25 .config0 = 0x00005682,
26 .rascas0 = 0x00000302,
27 .rdconfig = 0x00000011, /* undocumented but crucial value */
28
29 .trp = 83333333,
30 .tras = 23809524,
31 .tsrex = 12500000,
32 .twr = 83000000, /* tWR = tRDL = 2 CLK */
33 .trc = 15384616,
34 .trfc = 15384616,
35 .txsr = 12500000,
36 .trrd = 1,
37 .tmrd = 1,
38 .tcdlr = 0,
39
40 .refresh = 130000, /* 800 clock cycles */
41
42 .mode = 0x00018000,
43 .emode = 0x02000000,
44};
45
46void spl_board_init(void)
47{
48 /* First of all silence buzzer controlled by GPO_20 */
49 writel((1 << 20), &gpio->p3_outp_clr);
50
Trevor Woerner0b881ac2021-06-10 22:37:02 -040051 lpc32xx_uart_init(CONFIG_CONS_INDEX);
Vladimir Zapolskiy89f86a22015-07-18 01:47:11 +030052 preloader_console_init();
53
54 ddr_init(&dram_64mb);
55
56 /*
57 * NAND initialization is done by nand_init(),
58 * here just enable NAND SLC clocks
59 */
60 lpc32xx_slc_nand_init();
61}
62
63u32 spl_boot_device(void)
64{
65 return BOOT_DEVICE_NAND;
66}