| Masahiro Yamada | 144a3e0 | 2015-04-21 20:38:20 +0900 | [diff] [blame] | 1 | if ARCH_SOCFPGA |
| 2 | |
| Marek Vasut | 822e795 | 2015-08-02 21:57:57 +0200 | [diff] [blame] | 3 | config TARGET_SOCFPGA_ARRIA5 |
| 4 | bool |
| 5 | |
| 6 | config TARGET_SOCFPGA_CYCLONE5 |
| 7 | bool |
| 8 | |
| Masahiro Yamada | 144a3e0 | 2015-04-21 20:38:20 +0900 | [diff] [blame] | 9 | choice |
| 10 | prompt "Altera SOCFPGA board select" |
| Joe Hershberger | f069960 | 2015-05-12 14:46:23 -0500 | [diff] [blame] | 11 | optional |
| Masahiro Yamada | 144a3e0 | 2015-04-21 20:38:20 +0900 | [diff] [blame] | 12 | |
| Marek Vasut | 822e795 | 2015-08-02 21:57:57 +0200 | [diff] [blame] | 13 | config TARGET_SOCFPGA_ARRIA5_SOCDK |
| 14 | bool "Altera SOCFPGA SoCDK (Arria V)" |
| 15 | select TARGET_SOCFPGA_ARRIA5 |
| Masahiro Yamada | 144a3e0 | 2015-04-21 20:38:20 +0900 | [diff] [blame] | 16 | |
| Marek Vasut | 822e795 | 2015-08-02 21:57:57 +0200 | [diff] [blame] | 17 | config TARGET_SOCFPGA_CYCLONE5_SOCDK |
| 18 | bool "Altera SOCFPGA SoCDK (Cyclone V)" |
| 19 | select TARGET_SOCFPGA_CYCLONE5 |
| Masahiro Yamada | 144a3e0 | 2015-04-21 20:38:20 +0900 | [diff] [blame] | 20 | |
| Marek Vasut | 8e8b62a | 2015-08-03 01:37:28 +0200 | [diff] [blame] | 21 | config TARGET_SOCFPGA_DENX_MCVEVK |
| 22 | bool "DENX MCVEVK (Cyclone V)" |
| 23 | select TARGET_SOCFPGA_CYCLONE5 |
| 24 | |
| Dinh Nguyen | c3364da | 2015-09-01 17:41:52 -0500 | [diff] [blame] | 25 | config TARGET_SOCFPGA_TERASIC_DE0_NANO |
| 26 | bool "Terasic DE0-Nano-Atlas (Cyclone V)" |
| 27 | select TARGET_SOCFPGA_CYCLONE5 |
| 28 | |
| Marek Vasut | b415bad | 2015-06-21 17:28:53 +0200 | [diff] [blame] | 29 | config TARGET_SOCFPGA_TERASIC_SOCKIT |
| 30 | bool "Terasic SoCkit (Cyclone V)" |
| 31 | select TARGET_SOCFPGA_CYCLONE5 |
| 32 | |
| Masahiro Yamada | 144a3e0 | 2015-04-21 20:38:20 +0900 | [diff] [blame] | 33 | endchoice |
| 34 | |
| 35 | config SYS_BOARD |
| Marek Vasut | 3f4c561 | 2015-08-10 21:24:53 +0200 | [diff] [blame] | 36 | default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK |
| 37 | default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK |
| Dinh Nguyen | c3364da | 2015-09-01 17:41:52 -0500 | [diff] [blame] | 38 | default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO |
| Marek Vasut | 8e8b62a | 2015-08-03 01:37:28 +0200 | [diff] [blame] | 39 | default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK |
| Marek Vasut | b415bad | 2015-06-21 17:28:53 +0200 | [diff] [blame] | 40 | default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT |
| Masahiro Yamada | 144a3e0 | 2015-04-21 20:38:20 +0900 | [diff] [blame] | 41 | |
| 42 | config SYS_VENDOR |
| Marek Vasut | 822e795 | 2015-08-02 21:57:57 +0200 | [diff] [blame] | 43 | default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK |
| 44 | default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK |
| Marek Vasut | 8e8b62a | 2015-08-03 01:37:28 +0200 | [diff] [blame] | 45 | default "denx" if TARGET_SOCFPGA_DENX_MCVEVK |
| Dinh Nguyen | c3364da | 2015-09-01 17:41:52 -0500 | [diff] [blame] | 46 | default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO |
| Marek Vasut | b415bad | 2015-06-21 17:28:53 +0200 | [diff] [blame] | 47 | default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT |
| Masahiro Yamada | 144a3e0 | 2015-04-21 20:38:20 +0900 | [diff] [blame] | 48 | |
| 49 | config SYS_SOC |
| 50 | default "socfpga" |
| 51 | |
| 52 | config SYS_CONFIG_NAME |
| Dinh Nguyen | 16f6ffd | 2015-09-22 17:01:32 -0500 | [diff] [blame] | 53 | default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK |
| 54 | default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK |
| Dinh Nguyen | c3364da | 2015-09-01 17:41:52 -0500 | [diff] [blame] | 55 | default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO |
| Marek Vasut | 8e8b62a | 2015-08-03 01:37:28 +0200 | [diff] [blame] | 56 | default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK |
| Marek Vasut | b415bad | 2015-06-21 17:28:53 +0200 | [diff] [blame] | 57 | default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT |
| Masahiro Yamada | 144a3e0 | 2015-04-21 20:38:20 +0900 | [diff] [blame] | 58 | |
| 59 | endif |