Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 1 | /* |
| 2 | * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9rl.h] |
| 3 | * |
| 4 | * Copyright (C) 2007 Atmel Corporation |
| 5 | * |
| 6 | * Common definitions. |
| 7 | * Based on AT91SAM9RL datasheet revision A. (Preliminary) |
| 8 | * |
| 9 | * This file is subject to the terms and conditions of the GNU General Public |
| 10 | * License. See the file COPYING in the main directory of this archive for |
| 11 | * more details. |
| 12 | */ |
| 13 | |
| 14 | #ifndef AT91SAM9RL_H |
| 15 | #define AT91SAM9RL_H |
| 16 | |
| 17 | /* |
Xu, Hong | 16c092b | 2011-08-01 03:56:32 +0000 | [diff] [blame] | 18 | * defines to be used in other places |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 19 | */ |
Xu, Hong | 16c092b | 2011-08-01 03:56:32 +0000 | [diff] [blame] | 20 | #define CONFIG_AT91FAMILY /* it's a member of AT91 */ |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 21 | |
Xu, Hong | 16c092b | 2011-08-01 03:56:32 +0000 | [diff] [blame] | 22 | /* |
| 23 | * Peripheral identifiers/interrupts. |
| 24 | */ |
| 25 | #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ |
| 26 | #define ATMEL_ID_SYS 1 /* System Peripherals */ |
| 27 | #define ATMEL_ID_PIOA 2 /* Parallel IO Controller A */ |
| 28 | #define ATMEL_ID_PIOB 3 /* Parallel IO Controller B */ |
| 29 | #define ATMEL_ID_PIOC 4 /* Parallel IO Controller C */ |
| 30 | #define ATMEL_ID_PIOD 5 /* Parallel IO Controller D */ |
| 31 | #define ATMEL_ID_USART0 6 /* USART 0 */ |
| 32 | #define ATMEL_ID_USART1 7 /* USART 1 */ |
| 33 | #define ATMEL_ID_USART2 8 /* USART 2 */ |
| 34 | #define ATMEL_ID_USART3 9 /* USART 3 */ |
| 35 | #define ATMEL_ID_MCI 10 /* Multimedia Card Interface */ |
| 36 | #define ATMEL_ID_TWI0 11 /* TWI 0 */ |
| 37 | #define ATMEL_ID_TWI1 12 /* TWI 1 */ |
| 38 | #define ATMEL_ID_SPI 13 /* Serial Peripheral Interface */ |
| 39 | #define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */ |
| 40 | #define ATMEL_ID_SSC1 15 /* Serial Synchronous Controller 1 */ |
| 41 | #define ATMEL_ID_TC0 16 /* Timer Counter 0 */ |
| 42 | #define ATMEL_ID_TC1 17 /* Timer Counter 1 */ |
| 43 | #define ATMEL_ID_TC2 18 /* Timer Counter 2 */ |
| 44 | #define ATMEL_ID_PWMC 19 /* Pulse Width Modulation Controller */ |
| 45 | #define ATMEL_ID_TSC 20 /* Touch Screen Controller */ |
| 46 | #define ATMEL_ID_DMA 21 /* DMA Controller */ |
| 47 | #define ATMEL_ID_UDPHS 22 /* USB Device HS */ |
| 48 | #define ATMEL_ID_LCDC 23 /* LCD Controller */ |
| 49 | #define ATMEL_ID_AC97C 24 /* AC97 Controller */ |
| 50 | #define ATMEL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */ |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 51 | |
| 52 | /* |
| 53 | * User Peripheral physical base addresses. |
| 54 | */ |
Xu, Hong | 16c092b | 2011-08-01 03:56:32 +0000 | [diff] [blame] | 55 | #define ATMEL_BASE_TCB0 0xfffa0000 |
| 56 | #define ATMEL_BASE_TC0 0xfffa0000 |
| 57 | #define ATMEL_BASE_TC1 0xfffa0040 |
| 58 | #define ATMEL_BASE_TC2 0xfffa0080 |
| 59 | #define ATMEL_BASE_MCI 0xfffa4000 |
| 60 | #define ATMEL_BASE_TWI0 0xfffa8000 |
| 61 | #define ATMEL_BASE_TWI1 0xfffac000 |
| 62 | #define ATMEL_BASE_USART0 0xfffb0000 |
| 63 | #define ATMEL_BASE_USART1 0xfffb4000 |
| 64 | #define ATMEL_BASE_USART2 0xfffb8000 |
| 65 | #define ATMEL_BASE_USART3 0xfffbc000 |
| 66 | #define ATMEL_BASE_SSC0 0xfffc0000 |
| 67 | #define ATMEL_BASE_SSC1 0xfffc4000 |
| 68 | #define ATMEL_BASE_PWMC 0xfffc8000 |
| 69 | #define ATMEL_BASE_SPI0 0xfffcc000 |
| 70 | #define ATMEL_BASE_TSC 0xfffd0000 |
| 71 | #define ATMEL_BASE_UDPHS 0xfffd4000 |
| 72 | #define ATMEL_BASE_AC97C 0xfffd8000 |
| 73 | #define ATMEL_BASE_SYS 0xffffc000 |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 74 | |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 75 | /* |
Xu, Hong | 16c092b | 2011-08-01 03:56:32 +0000 | [diff] [blame] | 76 | * System Peripherals |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 77 | */ |
Xu, Hong | 16c092b | 2011-08-01 03:56:32 +0000 | [diff] [blame] | 78 | #define ATMEL_BASE_DMA 0xffffe600 |
| 79 | #define ATMEL_BASE_ECC 0xffffe800 |
| 80 | #define ATMEL_BASE_SDRAMC 0xffffea00 |
| 81 | #define ATMEL_BASE_SMC 0xffffec00 |
| 82 | #define ATMEL_BASE_MATRIX 0xffffee00 |
| 83 | #define ATMEL_BASE_CCFG 0xffffef10 |
| 84 | #define ATMEL_BASE_AIC 0xfffff000 |
| 85 | #define ATMEL_BASE_DBGU 0xfffff200 |
| 86 | #define ATMEL_BASE_PIOA 0xfffff400 |
| 87 | #define ATMEL_BASE_PIOB 0xfffff600 |
| 88 | #define ATMEL_BASE_PIOC 0xfffff800 |
| 89 | #define ATMEL_BASE_PIOD 0xfffffa00 |
| 90 | #define ATMEL_BASE_PMC 0xfffffc00 |
| 91 | #define ATMEL_BASE_RSTC 0xfffffd00 |
| 92 | #define ATMEL_BASE_SHDWC 0xfffffd10 |
| 93 | #define ATMEL_BASE_RTT 0xfffffd20 |
| 94 | #define ATMEL_BASE_PIT 0xfffffd30 |
| 95 | #define ATMEL_BASE_WDT 0xfffffd40 |
| 96 | #define ATMEL_BASE_SCKCR 0xfffffd50 |
| 97 | #define ATMEL_BASE_GPBR 0xfffffd60 |
| 98 | #define ATMEL_BASE_RTC 0xfffffe00 |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 99 | |
| 100 | /* |
| 101 | * Internal Memory. |
| 102 | */ |
Xu, Hong | 16c092b | 2011-08-01 03:56:32 +0000 | [diff] [blame] | 103 | #define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */ |
| 104 | #define ATMEL_BASE_ROM 0x00400000 /* Internal ROM base address */ |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 105 | |
Xu, Hong | 16c092b | 2011-08-01 03:56:32 +0000 | [diff] [blame] | 106 | #define ATMEL_BASE_LCDC 0x00500000 /* LCD Controller */ |
| 107 | #define ATMEL_UHP_BASE 0x00600000 /* USB Device HS controller */ |
| 108 | |
| 109 | /* |
| 110 | * External memory |
| 111 | */ |
| 112 | #define ATMEL_BASE_CS0 0x10000000 |
| 113 | #define ATMEL_BASE_CS1 0x20000000 /* SDRAM */ |
| 114 | #define ATMEL_BASE_CS2 0x30000000 |
| 115 | #define ATMEL_BASE_CS3 0x40000000 /* NAND */ |
| 116 | #define ATMEL_BASE_CS4 0x50000000 /* Compact Flash Slot 0 */ |
| 117 | #define ATMEL_BASE_CS5 0x60000000 /* Compact Flash Slot 1 */ |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 118 | |
Bo Shen | 568079a | 2015-02-04 15:53:01 +0800 | [diff] [blame] | 119 | /* Timer */ |
| 120 | #define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c |
| 121 | |
Xu, Hong | 16c092b | 2011-08-01 03:56:32 +0000 | [diff] [blame] | 122 | /* |
| 123 | * Other misc defines |
| 124 | */ |
| 125 | #define ATMEL_PIO_PORTS 4 /* this SoC has 4 PIO */ |
| 126 | #define ATMEL_BASE_PIO ATMEL_BASE_PIOA |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 127 | |
Jean-Christophe PLAGNIOL-VILLARD | b21aa66 | 2009-05-31 12:44:46 +0200 | [diff] [blame] | 128 | /* |
| 129 | * Cpu Name |
| 130 | */ |
Xu, Hong | 16c092b | 2011-08-01 03:56:32 +0000 | [diff] [blame] | 131 | #define ATMEL_CPU_NAME "AT91SAM9RL" |
Jean-Christophe PLAGNIOL-VILLARD | b21aa66 | 2009-05-31 12:44:46 +0200 | [diff] [blame] | 132 | |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 133 | #endif |