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git01.mediatek.com / filogic / uboot / 0a2bac788b93d3fa4b3e660838a9dad6b08cc2eb / . / include / configs / linkit-smart-7688.h
blob: 28372d41590a83ef65f780635ced2977a51c65ea [file] [log] [blame]
Stefan Roese2052a932018-08-16 15:27:30 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2018 Stefan Roese <sr@denx.de>
4 */
5
6#ifndef __CONFIG_LINKIT_SMART_7688_H
7#define __CONFIG_LINKIT_SMART_7688_H
8
Stefan Roese2052a932018-08-16 15:27:30 +0200[diff] [blame]9/* RAM */
10#define CONFIG_SYS_SDRAM_BASE 0x80000000
11
Stefan Roese2052a932018-08-16 15:27:30 +0200[diff] [blame]12#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
13
developer9720bc32020-04-21 09:28:48 +0200[diff] [blame]14/* SPL */
Stefan Roese2052a932018-08-16 15:27:30 +0200[diff] [blame]15
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame]16#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE
developer9720bc32020-04-21 09:28:48 +0200[diff] [blame]17
18/* Dummy value */
19#define CONFIG_SYS_UBOOT_BASE 0
20
21/* Serial SPL */
Simon Glassf4d60392021-08-08 12:20:12 -0600[diff] [blame]22#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
Tom Rinidf6a2152022-11-16 13:10:28 -0500[diff] [blame]23#define CFG_SYS_NS16550_CLK 40000000
24#define CFG_SYS_NS16550_COM3 0xb0000e00
developer9720bc32020-04-21 09:28:48 +0200[diff] [blame]25
26#endif
27
Stefan Roese2052a932018-08-16 15:27:30 +0200[diff] [blame]28/* UART */
29#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
developere1693432019-09-25 17:45:42 +0800[diff] [blame]30 230400, 460800, 921600 }
Stefan Roese2052a932018-08-16 15:27:30 +0200[diff] [blame]31
32/* RAM */
Stefan Roese2052a932018-08-16 15:27:30 +0200[diff] [blame]33
Stefan Roese2052a932018-08-16 15:27:30 +0200[diff] [blame]34/* Environment settings */
Stefan Roese2052a932018-08-16 15:27:30 +0200[diff] [blame]35
Stefan Roese2052a932018-08-16 15:27:30 +0200[diff] [blame]36#endif /* __CONFIG_LINKIT_SMART_7688_H */