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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +02002/*
3 * (C) Copyright 2008
4 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +02005 */
6
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +02007#include <common.h>
Simon Glass8e16b1e2019-12-28 10:45:05 -07008#include <init.h>
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +02009#include <asm/processor.h>
10#include <asm/immap_85xx.h>
York Sunf0626592013-09-30 09:22:09 -070011#include <fsl_ddr_sdram.h>
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020012#include <asm/processor.h>
13#include <asm/mmu.h>
14#include <spd_sdram.h>
Simon Glassdbd79542020-05-10 11:40:11 -060015#include <linux/delay.h>
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020016
17
18#if !defined(CONFIG_SPD_EEPROM)
19/*
20 * Autodetect onboard DDR SDRAM on 85xx platforms
21 *
22 * NOTE: Some of the hardcoded values are hardware dependant,
23 * so this should be extended for other future boards
24 * using this routine!
25 */
Becky Bruce5e35d8a2010-12-17 17:17:56 -060026phys_size_t fixed_sdram(void)
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020027{
York Suna21803d2013-11-18 10:29:32 -080028 struct ccsr_ddr __iomem *ddr =
Tom Rini376b88a2022-10-28 20:27:13 -040029 (struct ccsr_ddr __iomem *)(CFG_SYS_FSL_DDR_ADDR);
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020030
31 /*
32 * Disable memory controller.
33 */
34 ddr->cs0_config = 0;
35 ddr->sdram_cfg = 0;
36
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020037 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
38 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
39 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
40 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
41 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
42 ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
43 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
44 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONFIG_2;
45 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CONTROL;
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020046
47 asm ("sync;isync;msync");
48 udelay(1000);
49
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020050 ddr->sdram_cfg = CONFIG_SYS_DDR_CONFIG;
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020051 asm ("sync; isync; msync");
52 udelay(1000);
53
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020054 if (get_ram_size(0, CONFIG_SYS_SDRAM_SIZE<<20) == CONFIG_SYS_SDRAM_SIZE<<20) {
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020055 /*
56 * OK, size detected -> all done
57 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020058 return CONFIG_SYS_SDRAM_SIZE<<20;
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020059 }
60
61 return 0; /* nothing found ! */
62}
63#endif
64
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020065#if defined(CONFIG_SYS_DRAM_TEST)
Simon Glass0ffd9db2019-12-28 10:45:06 -070066int testdram(void)
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020067{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020068 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
69 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020070 uint *p;
71
72 printf ("SDRAM test phase 1:\n");
73 for (p = pstart; p < pend; p++)
74 *p = 0xaaaaaaaa;
75
76 for (p = pstart; p < pend; p++) {
77 if (*p != 0xaaaaaaaa) {
78 printf ("SDRAM test fails at: %08x\n", (uint) p);
79 return 1;
80 }
81 }
82
83 printf ("SDRAM test phase 2:\n");
84 for (p = pstart; p < pend; p++)
85 *p = 0x55555555;
86
87 for (p = pstart; p < pend; p++) {
88 if (*p != 0x55555555) {
89 printf ("SDRAM test fails at: %08x\n", (uint) p);
90 return 1;
91 }
92 }
93
94 printf ("SDRAM test passed.\n");
95 return 0;
96}
97#endif