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git01.mediatek.com / filogic / uboot / 0a1978917d60f9036072bdbfaf7c55508234ede2 / . / arch / powerpc / cpu / mpc85xx / t4240_serdes.c
blob: 74c4c81887c2b66507aef51ea2d761dd2a056e71 [file] [log] [blame]
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]4 * SPDX-License-Identifier: GPL-2.0+
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]5 */
6
7#include <common.h>
8#include <asm/fsl_serdes.h>
9#include <asm/processor.h>
10#include <asm/io.h>
11#include "fsl_corenet2_serdes.h"
12
13struct serdes_config {
14 u32 protocol;
15 u8 lanes[SRDS_MAX_LANES];
16};
17
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]18#ifdef CONFIG_PPC_T4240
York Sun85e660f2013-03-25 07:33:28 +0000[diff] [blame]19static const struct serdes_config serdes1_cfg_tbl[] = {
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]20 /* SerDes 1 */
21 {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
22 XAUI_FM1_MAC9, XAUI_FM1_MAC9,
23 XAUI_FM1_MAC10, XAUI_FM1_MAC10,
24 XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
25 {2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
26 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
27 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
28 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
29 {4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
30 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
31 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
32 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]33 {27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
34 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
35 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
36 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]37 {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
38 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
39 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
40 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]41 {35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
42 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
43 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
44 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]45 {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
46 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
47 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
48 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]49 {37, {NONE, NONE, QSGMII_FM1_B, NONE,
50 NONE, NONE, QSGMII_FM1_A, NONE} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]51 {38, {NONE, NONE, QSGMII_FM1_B, NONE,
52 NONE, NONE, QSGMII_FM1_A, NONE}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]53 {39, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
54 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
55 NONE, NONE, QSGMII_FM1_A, NONE} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]56 {40, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
57 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
58 NONE, NONE, QSGMII_FM1_A, NONE}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]59 {45, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
60 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
61 NONE, NONE, QSGMII_FM1_A, NONE} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]62 {46, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
63 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
64 NONE, NONE, QSGMII_FM1_A, NONE}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]65 {47, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
66 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
67 NONE, NONE, QSGMII_FM1_A, NONE} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]68 {48, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
69 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
70 NONE, NONE, QSGMII_FM1_A, NONE}},
71 {}
72};
York Sun85e660f2013-03-25 07:33:28 +0000[diff] [blame]73static const struct serdes_config serdes2_cfg_tbl[] = {
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]74 /* SerDes 2 */
75 {1, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
76 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
77 XAUI_FM2_MAC10, XAUI_FM2_MAC10,
78 XAUI_FM2_MAC10, XAUI_FM2_MAC10}},
79 {2, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
80 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
81 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
82 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
83 {4, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
84 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
85 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
86 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]87 {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
88 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
89 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
90 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]91 {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
92 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
93 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
94 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]95 {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
96 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
97 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
98 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]99 {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
100 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
101 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
102 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
103 {14, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
104 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
105 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
106 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]107 {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
108 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
109 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
110 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]111 {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
112 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
113 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
114 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]115 {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
116 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
117 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
118 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]119 {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
120 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
121 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
122 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
123 {23, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
124 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
125 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
126 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]127 {24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
128 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
129 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
130 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]131 {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
132 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
133 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
134 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
135 {26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
136 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
137 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
138 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]139 {27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
140 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
141 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
142 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]143 {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
144 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
145 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
146 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]147 {35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
148 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
149 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
150 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]151 {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
152 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
153 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
154 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]155 {37, {NONE, NONE, QSGMII_FM2_B, NONE,
156 NONE, NONE, QSGMII_FM2_A, NONE} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]157 {38, {NONE, NONE, QSGMII_FM2_B, NONE,
Shaohui Xiec218d292013-08-19 18:58:52 +0800[diff] [blame]158 NONE, NONE, QSGMII_FM2_A, NONE} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]159 {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
160 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
161 NONE, NONE, QSGMII_FM2_A, NONE} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]162 {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
163 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
Shaohui Xiec218d292013-08-19 18:58:52 +0800[diff] [blame]164 NONE, NONE, QSGMII_FM2_A, NONE} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]165 {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
166 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
167 NONE, NONE, QSGMII_FM2_A, NONE} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]168 {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
169 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
Shaohui Xiec218d292013-08-19 18:58:52 +0800[diff] [blame]170 NONE, NONE, QSGMII_FM2_A, NONE} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]171 {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
172 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
173 NONE, NONE, QSGMII_FM2_A, NONE} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]174 {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
175 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
Shaohui Xiec218d292013-08-19 18:58:52 +0800[diff] [blame]176 NONE, NONE, QSGMII_FM2_A, NONE} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]177 {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
178 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
179 NONE, NONE, QSGMII_FM2_A, NONE} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]180 {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
181 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
Shaohui Xiec218d292013-08-19 18:58:52 +0800[diff] [blame]182 NONE, NONE, QSGMII_FM2_A, NONE} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]183 {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
184 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
185 NONE, NONE, QSGMII_FM2_A, NONE} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]186 {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
187 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
Shaohui Xiec218d292013-08-19 18:58:52 +0800[diff] [blame]188 NONE, NONE, QSGMII_FM2_A, NONE} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]189 {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
190 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
191 NONE, NONE, QSGMII_FM2_A, NONE} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]192 {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
193 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
Shaohui Xiec218d292013-08-19 18:58:52 +0800[diff] [blame]194 NONE, NONE, QSGMII_FM2_A, NONE} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]195 {55, {XFI_FM1_MAC9, XFI_FM1_MAC10,
196 XFI_FM2_MAC10, XFI_FM2_MAC9,
197 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
198 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]199 {56, {XFI_FM1_MAC9, XFI_FM1_MAC10,
200 XFI_FM2_MAC10, XFI_FM2_MAC9,
201 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
202 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
203 {57, {XFI_FM1_MAC9, XFI_FM1_MAC10,
204 XFI_FM2_MAC10, XFI_FM2_MAC9,
205 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
206 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
207 {}
208};
York Sun85e660f2013-03-25 07:33:28 +0000[diff] [blame]209static const struct serdes_config serdes3_cfg_tbl[] = {
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]210 /* SerDes 3 */
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]211 {1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]212 {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]213 {3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]214 {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]215 {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]216 {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]217 {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]218 {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE}},
219 {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
220 INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
221 {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
222 INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]223 {11, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
224 PCIE2, PCIE2, PCIE2, PCIE2} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]225 {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
226 PCIE2, PCIE2, PCIE2, PCIE2}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]227 {13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
228 PCIE2, PCIE2, PCIE2, PCIE2} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]229 {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
230 PCIE2, PCIE2, PCIE2, PCIE2}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]231 {15, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
232 SRIO1, SRIO1, SRIO1, SRIO1} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]233 {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
234 SRIO1, SRIO1, SRIO1, SRIO1}},
235 {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
236 SRIO1, SRIO1, SRIO1, SRIO1}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]237 {18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
238 SRIO1, SRIO1, SRIO1, SRIO1} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]239 {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
240 SRIO1, SRIO1, SRIO1, SRIO1}},
241 {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
242 SRIO1, SRIO1, SRIO1, SRIO1}},
243 {}
244};
York Sun85e660f2013-03-25 07:33:28 +0000[diff] [blame]245static const struct serdes_config serdes4_cfg_tbl[] = {
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]246 /* SerDes 4 */
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]247 {1, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]248 {2, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]249 {3, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]250 {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]251 {5, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]252 {6, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]253 {7, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]254 {8, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]255 {9, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} },
Roy Zangcc117ce2013-03-25 07:33:18 +0000[diff] [blame]256 {10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]257 {11, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} },
Roy Zangcc117ce2013-03-25 07:33:18 +0000[diff] [blame]258 {12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]259 {13, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]260 {14, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]261 {15, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} },
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]262 {16, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
263 {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
264 {}
265};
Shengzhou Liu26ed2d02014-04-25 16:31:22 +0800[diff] [blame]266#elif defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080)
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]267static const struct serdes_config serdes1_cfg_tbl[] = {
268 /* SerDes 1 */
269 {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
270 XAUI_FM1_MAC9, XAUI_FM1_MAC9,
271 XAUI_FM1_MAC10, XAUI_FM1_MAC10,
272 XAUI_FM1_MAC10, XAUI_FM1_MAC10} },
273 {2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
274 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
275 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
276 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
277 {4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
278 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
279 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
280 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]281 {27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
282 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
283 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
284 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]285 {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
286 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
287 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
288 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]289 {35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
290 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
291 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
292 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]293 {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
294 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
295 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
296 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]297 {37, {NONE, NONE, QSGMII_FM1_B, NONE,
298 NONE, NONE, QSGMII_FM1_A, NONE} },
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]299 {38, {NONE, NONE, QSGMII_FM1_B, NONE,
300 NONE, NONE, QSGMII_FM1_A, NONE} },
301 {}
302};
303static const struct serdes_config serdes2_cfg_tbl[] = {
304 /* SerDes 2 */
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]305 {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
306 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
307 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
308 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]309 {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
310 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
311 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
312 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]313 {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
314 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
315 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
316 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]317 {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
318 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
319 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
320 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]321 {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
322 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
323 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
324 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]325 {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
326 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
327 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
328 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]329 {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
330 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
331 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
332 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]333 {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
334 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
335 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
336 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]337 {24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
338 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
339 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
340 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]341 {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
342 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
343 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
344 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
345 {26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
346 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
347 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
348 NONE, NONE} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]349 {27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
350 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
351 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
352 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]353 {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
354 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
355 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
356 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]357 {35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
358 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
359 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
360 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]361 {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
362 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
363 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
364 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]365 {37, {NONE, NONE, QSGMII_FM2_B, NONE,
366 NONE, QSGMII_FM1_A, NONE, NONE} },
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]367 {38, {NONE, NONE, QSGMII_FM2_B, NONE,
368 NONE, QSGMII_FM1_A, NONE, NONE} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]369 {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
370 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
371 NONE, QSGMII_FM1_A, NONE, NONE} },
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]372 {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
373 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
374 NONE, QSGMII_FM1_A, NONE, NONE} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]375 {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
376 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
377 NONE, QSGMII_FM1_A, NONE, NONE} },
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]378 {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
379 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
380 NONE, QSGMII_FM1_A, NONE, NONE} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]381 {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
382 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
383 NONE, QSGMII_FM1_A, NONE, NONE} },
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]384 {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
385 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
386 NONE, QSGMII_FM1_A, NONE, NONE} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]387 {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
388 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
389 NONE, NONE, NONE, NONE} },
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]390 {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
391 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
392 NONE, NONE, NONE, NONE} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]393 {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
394 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
395 NONE, NONE, NONE, NONE} },
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]396 {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
397 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
398 NONE, NONE, NONE, NONE} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]399 {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
400 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
401 NONE, NONE, NONE, NONE} },
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]402 {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
403 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
404 NONE, NONE, NONE, NONE} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]405 {55, {NONE, XFI_FM1_MAC10,
406 XFI_FM2_MAC10, NONE,
407 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
408 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]409 {56, {NONE, XFI_FM1_MAC10,
410 XFI_FM2_MAC10, NONE,
411 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
412 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
413 {57, {NONE, XFI_FM1_MAC10,
414 XFI_FM2_MAC10, NONE,
415 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
416 NONE, NONE} },
417 {}
418};
419static const struct serdes_config serdes3_cfg_tbl[] = {
420 /* SerDes 3 */
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]421 {1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]422 {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]423 {3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]424 {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]425 {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]426 {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]427 {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]428 {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
429 {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
430 INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
431 {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
432 INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]433 {11, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
434 PCIE2, PCIE2, PCIE2, PCIE2} },
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]435 {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
436 PCIE2, PCIE2, PCIE2, PCIE2} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]437 {13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
438 PCIE2, PCIE2, PCIE2, PCIE2} },
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]439 {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
440 PCIE2, PCIE2, PCIE2, PCIE2} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]441 {15, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
442 SRIO1, SRIO1, SRIO1, SRIO1} },
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]443 {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
444 SRIO1, SRIO1, SRIO1, SRIO1} },
445 {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
446 SRIO1, SRIO1, SRIO1, SRIO1} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]447 {18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
448 SRIO1, SRIO1, SRIO1, SRIO1} },
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]449 {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
450 SRIO1, SRIO1, SRIO1, SRIO1} },
451 {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
452 NONE, NONE, NONE, NONE} },
453 {}
454};
455static const struct serdes_config serdes4_cfg_tbl[] = {
456 /* SerDes 4 */
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]457 {3, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]458 {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]459 {5, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]460 {6, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]461 {7, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]462 {8, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]463 {9, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} },
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]464 {10, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]465 {11, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} },
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]466 {12, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]467 {13, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]468 {14, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800[diff] [blame]469 {15, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
York Sunfb5137a2013-03-25 07:33:29 +0000[diff] [blame]470 {16, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
471 {18, {AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA} },
472 {}
473}
474;
475#else
476#error "Need to define SerDes protocol"
477#endif
York Sun85e660f2013-03-25 07:33:28 +0000[diff] [blame]478static const struct serdes_config *serdes_cfg_tbl[] = {
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]479 serdes1_cfg_tbl,
480 serdes2_cfg_tbl,
481 serdes3_cfg_tbl,
482 serdes4_cfg_tbl,
483};
484
485enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
486{
York Sun85e660f2013-03-25 07:33:28 +0000[diff] [blame]487 const struct serdes_config *ptr;
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]488
489 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
490 return 0;
491
492 ptr = serdes_cfg_tbl[serdes];
493 while (ptr->protocol) {
494 if (ptr->protocol == cfg)
495 return ptr->lanes[lane];
496 ptr++;
497 }
498 return 0;
499}
500
501int is_serdes_prtcl_valid(int serdes, u32 prtcl)
502{
503 int i;
York Sun85e660f2013-03-25 07:33:28 +0000[diff] [blame]504 const struct serdes_config *ptr;
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]505
506 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
507 return 0;
508
509 ptr = serdes_cfg_tbl[serdes];
510 while (ptr->protocol) {
511 if (ptr->protocol == prtcl)
512 break;
513 ptr++;
514 }
515
516 if (!ptr->protocol)
517 return 0;
518
519 for (i = 0; i < SRDS_MAX_LANES; i++) {
520 if (ptr->lanes[i] != NONE)
521 return 1;
522 }
523
524 return 0;
525}