wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 1 | /* |
Wolfgang Denk | 331dfe8 | 2008-03-26 15:38:47 +0100 | [diff] [blame] | 2 | * (C) Copyright 2001-2008 |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * Keith Outwater, keith_outwater@mvis.com` |
| 5 | * |
| 6 | * See file CREDITS for list of people who contributed to this |
| 7 | * project. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of |
| 12 | * the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 22 | * MA 02111-1307 USA |
| 23 | */ |
| 24 | |
| 25 | /* |
| 26 | * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim) |
| 27 | * DS1337 Real Time Clock (RTC). |
| 28 | */ |
| 29 | |
| 30 | #include <common.h> |
| 31 | #include <command.h> |
| 32 | #include <rtc.h> |
| 33 | #include <i2c.h> |
| 34 | |
Michal Simek | c3e6c55 | 2008-07-14 19:45:37 +0200 | [diff] [blame] | 35 | #if defined(CONFIG_CMD_DATE) |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 36 | |
| 37 | /*---------------------------------------------------------------------*/ |
| 38 | #undef DEBUG_RTC |
| 39 | |
| 40 | #ifdef DEBUG_RTC |
| 41 | #define DEBUGR(fmt,args...) printf(fmt ,##args) |
| 42 | #else |
| 43 | #define DEBUGR(fmt,args...) |
| 44 | #endif |
| 45 | /*---------------------------------------------------------------------*/ |
| 46 | |
| 47 | /* |
| 48 | * RTC register addresses |
| 49 | */ |
| 50 | #define RTC_SEC_REG_ADDR 0x0 |
| 51 | #define RTC_MIN_REG_ADDR 0x1 |
| 52 | #define RTC_HR_REG_ADDR 0x2 |
| 53 | #define RTC_DAY_REG_ADDR 0x3 |
| 54 | #define RTC_DATE_REG_ADDR 0x4 |
| 55 | #define RTC_MON_REG_ADDR 0x5 |
| 56 | #define RTC_YR_REG_ADDR 0x6 |
| 57 | #define RTC_CTL_REG_ADDR 0x0e |
| 58 | #define RTC_STAT_REG_ADDR 0x0f |
| 59 | |
| 60 | /* |
| 61 | * RTC control register bits |
| 62 | */ |
Wolfgang Denk | 331dfe8 | 2008-03-26 15:38:47 +0100 | [diff] [blame] | 63 | #define RTC_CTL_BIT_A1IE 0x1 /* Alarm 1 interrupt enable */ |
| 64 | #define RTC_CTL_BIT_A2IE 0x2 /* Alarm 2 interrupt enable */ |
| 65 | #define RTC_CTL_BIT_INTCN 0x4 /* Interrupt control */ |
| 66 | #define RTC_CTL_BIT_RS1 0x8 /* Rate select 1 */ |
| 67 | #define RTC_CTL_BIT_RS2 0x10 /* Rate select 2 */ |
| 68 | #define RTC_CTL_BIT_DOSC 0x80 /* Disable Oscillator */ |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 69 | |
| 70 | /* |
| 71 | * RTC status register bits |
| 72 | */ |
Wolfgang Denk | 331dfe8 | 2008-03-26 15:38:47 +0100 | [diff] [blame] | 73 | #define RTC_STAT_BIT_A1F 0x1 /* Alarm 1 flag */ |
| 74 | #define RTC_STAT_BIT_A2F 0x2 /* Alarm 2 flag */ |
| 75 | #define RTC_STAT_BIT_OSF 0x80 /* Oscillator stop flag */ |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 76 | |
| 77 | |
| 78 | static uchar rtc_read (uchar reg); |
| 79 | static void rtc_write (uchar reg, uchar val); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 80 | |
| 81 | /* |
| 82 | * Get the current time from the RTC |
| 83 | */ |
Yuri Tikhonov | 9bacd94 | 2008-03-20 17:56:04 +0300 | [diff] [blame] | 84 | int rtc_get (struct rtc_time *tmp) |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 85 | { |
Yuri Tikhonov | 9bacd94 | 2008-03-20 17:56:04 +0300 | [diff] [blame] | 86 | int rel = 0; |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 87 | uchar sec, min, hour, mday, wday, mon_cent, year, control, status; |
| 88 | |
| 89 | control = rtc_read (RTC_CTL_REG_ADDR); |
| 90 | status = rtc_read (RTC_STAT_REG_ADDR); |
| 91 | sec = rtc_read (RTC_SEC_REG_ADDR); |
| 92 | min = rtc_read (RTC_MIN_REG_ADDR); |
| 93 | hour = rtc_read (RTC_HR_REG_ADDR); |
| 94 | wday = rtc_read (RTC_DAY_REG_ADDR); |
| 95 | mday = rtc_read (RTC_DATE_REG_ADDR); |
| 96 | mon_cent = rtc_read (RTC_MON_REG_ADDR); |
| 97 | year = rtc_read (RTC_YR_REG_ADDR); |
| 98 | |
| 99 | DEBUGR ("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x " |
| 100 | "hr: %02x min: %02x sec: %02x control: %02x status: %02x\n", |
| 101 | year, mon_cent, mday, wday, hour, min, sec, control, status); |
| 102 | |
| 103 | if (status & RTC_STAT_BIT_OSF) { |
| 104 | printf ("### Warning: RTC oscillator has stopped\n"); |
| 105 | /* clear the OSF flag */ |
| 106 | rtc_write (RTC_STAT_REG_ADDR, |
| 107 | rtc_read (RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF); |
Yuri Tikhonov | 9bacd94 | 2008-03-20 17:56:04 +0300 | [diff] [blame] | 108 | rel = -1; |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 109 | } |
| 110 | |
| 111 | tmp->tm_sec = bcd2bin (sec & 0x7F); |
| 112 | tmp->tm_min = bcd2bin (min & 0x7F); |
| 113 | tmp->tm_hour = bcd2bin (hour & 0x3F); |
| 114 | tmp->tm_mday = bcd2bin (mday & 0x3F); |
| 115 | tmp->tm_mon = bcd2bin (mon_cent & 0x1F); |
| 116 | tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 2000 : 1900); |
| 117 | tmp->tm_wday = bcd2bin ((wday - 1) & 0x07); |
| 118 | tmp->tm_yday = 0; |
| 119 | tmp->tm_isdst= 0; |
| 120 | |
| 121 | DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", |
| 122 | tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, |
| 123 | tmp->tm_hour, tmp->tm_min, tmp->tm_sec); |
Yuri Tikhonov | 9bacd94 | 2008-03-20 17:56:04 +0300 | [diff] [blame] | 124 | |
| 125 | return rel; |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 126 | } |
| 127 | |
| 128 | |
| 129 | /* |
| 130 | * Set the RTC |
| 131 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 97a2e10 | 2008-09-01 23:06:23 +0200 | [diff] [blame] | 132 | int rtc_set (struct rtc_time *tmp) |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 133 | { |
| 134 | uchar century; |
| 135 | |
| 136 | DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", |
| 137 | tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, |
| 138 | tmp->tm_hour, tmp->tm_min, tmp->tm_sec); |
| 139 | |
| 140 | rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100)); |
| 141 | |
| 142 | century = (tmp->tm_year >= 2000) ? 0x80 : 0; |
| 143 | rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon) | century); |
| 144 | |
| 145 | rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1)); |
| 146 | rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday)); |
| 147 | rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour)); |
| 148 | rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min)); |
| 149 | rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec)); |
Jean-Christophe PLAGNIOL-VILLARD | 97a2e10 | 2008-09-01 23:06:23 +0200 | [diff] [blame] | 150 | |
| 151 | return 0; |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 152 | } |
| 153 | |
| 154 | |
| 155 | /* |
| 156 | * Reset the RTC. We also enable the oscillator output on the |
| 157 | * SQW/INTB* pin and program it for 32,768 Hz output. Note that |
| 158 | * according to the datasheet, turning on the square wave output |
| 159 | * increases the current drain on the backup battery from about |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 160 | * 600 nA to 2uA. Define CONFIG_SYS_RTC_DS1337_NOOSC if you wish to turn |
Joakim Tjernlund | 2ef2731 | 2008-03-26 13:02:13 +0100 | [diff] [blame] | 161 | * off the OSC output. |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 162 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 163 | #ifdef CONFIG_SYS_RTC_DS1337_NOOSC |
Joakim Tjernlund | 2ef2731 | 2008-03-26 13:02:13 +0100 | [diff] [blame] | 164 | #define RTC_DS1337_RESET_VAL \ |
Wolfgang Denk | 331dfe8 | 2008-03-26 15:38:47 +0100 | [diff] [blame] | 165 | (RTC_CTL_BIT_INTCN | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2) |
Joakim Tjernlund | 2ef2731 | 2008-03-26 13:02:13 +0100 | [diff] [blame] | 166 | #else |
| 167 | #define RTC_DS1337_RESET_VAL (RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2) |
| 168 | #endif |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 169 | void rtc_reset (void) |
| 170 | { |
Joakim Tjernlund | 2ef2731 | 2008-03-26 13:02:13 +0100 | [diff] [blame] | 171 | rtc_write (RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 172 | } |
| 173 | |
| 174 | |
| 175 | /* |
| 176 | * Helper functions |
| 177 | */ |
| 178 | |
| 179 | static |
| 180 | uchar rtc_read (uchar reg) |
| 181 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 182 | return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 183 | } |
| 184 | |
| 185 | |
| 186 | static void rtc_write (uchar reg, uchar val) |
| 187 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 188 | i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 189 | } |
| 190 | |
Jon Loeliger | 07efe2a | 2007-07-10 10:27:39 -0500 | [diff] [blame] | 191 | #endif |