wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 1 | /* |
Wolfgang Grandegger | 328c6ec | 2008-06-05 13:12:07 +0200 | [diff] [blame] | 2 | * (C) Copyright 2008 Wolfgang Grandegger <wg@denx.de> |
| 3 | * |
| 4 | * (C) Copyright 2006 |
| 5 | * Thomas Waehner, TQ-Systems GmbH, thomas.waehner@tqs.de. |
| 6 | * |
Stefan Roese | 0955402 | 2005-11-30 13:06:40 +0100 | [diff] [blame] | 7 | * (C) Copyright 2005 |
| 8 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 9 | * |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 10 | * Copyright 2004 Freescale Semiconductor. |
| 11 | * (C) Copyright 2002,2003, Motorola Inc. |
| 12 | * Xianghua Xiao, (X.Xiao@motorola.com) |
| 13 | * |
| 14 | * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> |
| 15 | * |
| 16 | * See file CREDITS for list of people who contributed to this |
| 17 | * project. |
| 18 | * |
| 19 | * This program is free software; you can redistribute it and/or |
| 20 | * modify it under the terms of the GNU General Public License as |
| 21 | * published by the Free Software Foundation; either version 2 of |
| 22 | * the License, or (at your option) any later version. |
| 23 | * |
| 24 | * This program is distributed in the hope that it will be useful, |
| 25 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
Wolfgang Denk | 82f15f3 | 2008-11-02 16:14:22 +0100 | [diff] [blame] | 26 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 27 | * GNU General Public License for more details. |
| 28 | * |
| 29 | * You should have received a copy of the GNU General Public License |
| 30 | * along with this program; if not, write to the Free Software |
| 31 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 32 | * MA 02111-1307 USA |
| 33 | */ |
| 34 | |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 35 | #include <common.h> |
| 36 | #include <pci.h> |
| 37 | #include <asm/processor.h> |
| 38 | #include <asm/immap_85xx.h> |
Kumar Gala | 9bbd643 | 2009-04-02 13:22:48 -0500 | [diff] [blame] | 39 | #include <asm/fsl_pci.h> |
Wolfgang Grandegger | c5809d7 | 2008-06-05 13:12:05 +0200 | [diff] [blame] | 40 | #include <asm/io.h> |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 41 | #include <ioports.h> |
Stefan Roese | 0955402 | 2005-11-30 13:06:40 +0100 | [diff] [blame] | 42 | #include <flash.h> |
Wolfgang Grandegger | f5be52d | 2008-06-05 13:12:06 +0200 | [diff] [blame] | 43 | #include <libfdt.h> |
| 44 | #include <fdt_support.h> |
Ben Warren | 052a5ea | 2008-08-31 20:37:00 -0700 | [diff] [blame] | 45 | #include <netdev.h> |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 46 | |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 47 | DECLARE_GLOBAL_DATA_PTR; |
| 48 | |
Stefan Roese | 0955402 | 2005-11-30 13:06:40 +0100 | [diff] [blame] | 49 | extern flash_info_t flash_info[]; /* FLASH chips info */ |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 50 | |
| 51 | void local_bus_init (void); |
Stefan Roese | 896391f | 2006-03-01 17:00:49 +0100 | [diff] [blame] | 52 | ulong flash_get_size (ulong base, int banknum); |
Wolfgang Denk | 31560d1 | 2006-07-21 15:24:56 +0200 | [diff] [blame] | 53 | |
Wolfgang Denk | 2df0053 | 2006-07-19 14:49:35 +0200 | [diff] [blame] | 54 | #ifdef CONFIG_PS2MULT |
Wolfgang Grandegger | 9039ce1 | 2008-06-05 13:12:00 +0200 | [diff] [blame] | 55 | void ps2mult_early_init (void); |
Wolfgang Denk | 2df0053 | 2006-07-19 14:49:35 +0200 | [diff] [blame] | 56 | #endif |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 57 | |
Stefan Roese | 0955402 | 2005-11-30 13:06:40 +0100 | [diff] [blame] | 58 | #ifdef CONFIG_CPM2 |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 59 | /* |
| 60 | * I/O Port configuration table |
| 61 | * |
| 62 | * if conf is 1, then that port pin will be configured at boot time |
| 63 | * according to the five values podr/pdir/ppar/psor/pdat for that entry |
| 64 | */ |
| 65 | |
| 66 | const iop_conf_t iop_conf_tab[4][32] = { |
| 67 | |
Wolfgang Grandegger | 9039ce1 | 2008-06-05 13:12:00 +0200 | [diff] [blame] | 68 | /* Port A: conf, ppar, psor, pdir, podr, pdat */ |
| 69 | { |
| 70 | {1, 1, 1, 0, 0, 0}, /* PA31: FCC1 MII COL */ |
| 71 | {1, 1, 1, 0, 0, 0}, /* PA30: FCC1 MII CRS */ |
| 72 | {1, 1, 1, 1, 0, 0}, /* PA29: FCC1 MII TX_ER */ |
| 73 | {1, 1, 1, 1, 0, 0}, /* PA28: FCC1 MII TX_EN */ |
| 74 | {1, 1, 1, 0, 0, 0}, /* PA27: FCC1 MII RX_DV */ |
| 75 | {1, 1, 1, 0, 0, 0}, /* PA26: FCC1 MII RX_ER */ |
| 76 | {0, 1, 0, 1, 0, 0}, /* PA25: FCC1 ATMTXD[0] */ |
| 77 | {0, 1, 0, 1, 0, 0}, /* PA24: FCC1 ATMTXD[1] */ |
| 78 | {0, 1, 0, 1, 0, 0}, /* PA23: FCC1 ATMTXD[2] */ |
| 79 | {0, 1, 0, 1, 0, 0}, /* PA22: FCC1 ATMTXD[3] */ |
| 80 | {1, 1, 0, 1, 0, 0}, /* PA21: FCC1 MII TxD[3] */ |
| 81 | {1, 1, 0, 1, 0, 0}, /* PA20: FCC1 MII TxD[2] */ |
| 82 | {1, 1, 0, 1, 0, 0}, /* PA19: FCC1 MII TxD[1] */ |
| 83 | {1, 1, 0, 1, 0, 0}, /* PA18: FCC1 MII TxD[0] */ |
| 84 | {1, 1, 0, 0, 0, 0}, /* PA17: FCC1 MII RxD[0] */ |
| 85 | {1, 1, 0, 0, 0, 0}, /* PA16: FCC1 MII RxD[1] */ |
| 86 | {1, 1, 0, 0, 0, 0}, /* PA15: FCC1 MII RxD[2] */ |
| 87 | {1, 1, 0, 0, 0, 0}, /* PA14: FCC1 MII RxD[3] */ |
| 88 | {0, 1, 0, 0, 0, 0}, /* PA13: FCC1 ATMRXD[3] */ |
| 89 | {0, 1, 0, 0, 0, 0}, /* PA12: FCC1 ATMRXD[2] */ |
| 90 | {0, 1, 0, 0, 0, 0}, /* PA11: FCC1 ATMRXD[1] */ |
| 91 | {0, 1, 0, 0, 0, 0}, /* PA10: FCC1 ATMRXD[0] */ |
| 92 | {0, 1, 1, 1, 0, 0}, /* PA9 : FCC1 L1TXD */ |
| 93 | {0, 1, 1, 0, 0, 0}, /* PA8 : FCC1 L1RXD */ |
| 94 | {0, 0, 0, 1, 0, 0}, /* PA7 : PA7 */ |
| 95 | {0, 1, 1, 1, 0, 0}, /* PA6 : TDM A1 L1RSYNC */ |
| 96 | {0, 0, 0, 1, 0, 0}, /* PA5 : PA5 */ |
| 97 | {0, 0, 0, 1, 0, 0}, /* PA4 : PA4 */ |
| 98 | {0, 0, 0, 1, 0, 0}, /* PA3 : PA3 */ |
| 99 | {0, 0, 0, 1, 0, 0}, /* PA2 : PA2 */ |
| 100 | {0, 0, 0, 0, 0, 0}, /* PA1 : FREERUN */ |
| 101 | {0, 0, 0, 1, 0, 0} /* PA0 : PA0 */ |
| 102 | }, |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 103 | |
Wolfgang Grandegger | 9039ce1 | 2008-06-05 13:12:00 +0200 | [diff] [blame] | 104 | /* Port B: conf, ppar, psor, pdir, podr, pdat */ |
| 105 | { |
| 106 | {1, 1, 0, 1, 0, 0}, /* PB31: FCC2 MII TX_ER */ |
| 107 | {1, 1, 0, 0, 0, 0}, /* PB30: FCC2 MII RX_DV */ |
| 108 | {1, 1, 1, 1, 0, 0}, /* PB29: FCC2 MII TX_EN */ |
| 109 | {1, 1, 0, 0, 0, 0}, /* PB28: FCC2 MII RX_ER */ |
| 110 | {1, 1, 0, 0, 0, 0}, /* PB27: FCC2 MII COL */ |
| 111 | {1, 1, 0, 0, 0, 0}, /* PB26: FCC2 MII CRS */ |
| 112 | {1, 1, 0, 1, 0, 0}, /* PB25: FCC2 MII TxD[3] */ |
| 113 | {1, 1, 0, 1, 0, 0}, /* PB24: FCC2 MII TxD[2] */ |
| 114 | {1, 1, 0, 1, 0, 0}, /* PB23: FCC2 MII TxD[1] */ |
| 115 | {1, 1, 0, 1, 0, 0}, /* PB22: FCC2 MII TxD[0] */ |
| 116 | {1, 1, 0, 0, 0, 0}, /* PB21: FCC2 MII RxD[0] */ |
| 117 | {1, 1, 0, 0, 0, 0}, /* PB20: FCC2 MII RxD[1] */ |
| 118 | {1, 1, 0, 0, 0, 0}, /* PB19: FCC2 MII RxD[2] */ |
| 119 | {1, 1, 0, 0, 0, 0}, /* PB18: FCC2 MII RxD[3] */ |
| 120 | {1, 1, 0, 0, 0, 0}, /* PB17: FCC3:RX_DIV */ |
| 121 | {1, 1, 0, 0, 0, 0}, /* PB16: FCC3:RX_ERR */ |
| 122 | {1, 1, 0, 1, 0, 0}, /* PB15: FCC3:TX_ERR */ |
| 123 | {1, 1, 0, 1, 0, 0}, /* PB14: FCC3:TX_EN */ |
| 124 | {1, 1, 0, 0, 0, 0}, /* PB13: FCC3:COL */ |
| 125 | {1, 1, 0, 0, 0, 0}, /* PB12: FCC3:CRS */ |
| 126 | {1, 1, 0, 0, 0, 0}, /* PB11: FCC3:RXD */ |
| 127 | {1, 1, 0, 0, 0, 0}, /* PB10: FCC3:RXD */ |
| 128 | {1, 1, 0, 0, 0, 0}, /* PB9 : FCC3:RXD */ |
| 129 | {1, 1, 0, 0, 0, 0}, /* PB8 : FCC3:RXD */ |
| 130 | {1, 1, 0, 1, 0, 0}, /* PB7 : FCC3:TXD */ |
| 131 | {1, 1, 0, 1, 0, 0}, /* PB6 : FCC3:TXD */ |
| 132 | {1, 1, 0, 1, 0, 0}, /* PB5 : FCC3:TXD */ |
| 133 | {1, 1, 0, 1, 0, 0}, /* PB4 : FCC3:TXD */ |
| 134 | {0, 0, 0, 0, 0, 0}, /* PB3 : pin doesn't exist */ |
| 135 | {0, 0, 0, 0, 0, 0}, /* PB2 : pin doesn't exist */ |
| 136 | {0, 0, 0, 0, 0, 0}, /* PB1 : pin doesn't exist */ |
| 137 | {0, 0, 0, 0, 0, 0} /* PB0 : pin doesn't exist */ |
| 138 | }, |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 139 | |
Wolfgang Grandegger | 9039ce1 | 2008-06-05 13:12:00 +0200 | [diff] [blame] | 140 | /* Port C: conf, ppar, psor, pdir, podr, pdat */ |
| 141 | { |
| 142 | {0, 0, 0, 1, 0, 0}, /* PC31: PC31 */ |
| 143 | {0, 0, 0, 1, 0, 0}, /* PC30: PC30 */ |
| 144 | {0, 1, 1, 0, 0, 0}, /* PC29: SCC1 EN *CLSN */ |
| 145 | {0, 0, 0, 1, 0, 0}, /* PC28: PC28 */ |
| 146 | {0, 0, 0, 1, 0, 0}, /* PC27: UART Clock in */ |
| 147 | {0, 0, 0, 1, 0, 0}, /* PC26: PC26 */ |
| 148 | {0, 0, 0, 1, 0, 0}, /* PC25: PC25 */ |
| 149 | {0, 0, 0, 1, 0, 0}, /* PC24: PC24 */ |
| 150 | {0, 1, 0, 1, 0, 0}, /* PC23: ATMTFCLK */ |
| 151 | {0, 1, 0, 0, 0, 0}, /* PC22: ATMRFCLK */ |
| 152 | {1, 1, 0, 0, 0, 0}, /* PC21: SCC1 EN RXCLK */ |
| 153 | {1, 1, 0, 0, 0, 0}, /* PC20: SCC1 EN TXCLK */ |
| 154 | {1, 1, 0, 0, 0, 0}, /* PC19: FCC2 MII RX_CLK CLK13 */ |
| 155 | {1, 1, 0, 0, 0, 0}, /* PC18: FCC Tx Clock (CLK14) */ |
| 156 | {1, 1, 0, 0, 0, 0}, /* PC17: PC17 */ |
| 157 | {1, 1, 0, 0, 0, 0}, /* PC16: FCC Tx Clock (CLK16) */ |
| 158 | {0, 1, 0, 0, 0, 0}, /* PC15: PC15 */ |
| 159 | {0, 1, 0, 0, 0, 0}, /* PC14: SCC1 EN *CD */ |
| 160 | {0, 1, 0, 0, 0, 0}, /* PC13: PC13 */ |
| 161 | {0, 1, 0, 1, 0, 0}, /* PC12: PC12 */ |
| 162 | {0, 0, 0, 1, 0, 0}, /* PC11: LXT971 transmit control */ |
| 163 | {0, 0, 0, 1, 0, 0}, /* PC10: FETHMDC */ |
| 164 | {0, 0, 0, 0, 0, 0}, /* PC9 : FETHMDIO */ |
| 165 | {0, 0, 0, 1, 0, 0}, /* PC8 : PC8 */ |
| 166 | {0, 0, 0, 1, 0, 0}, /* PC7 : PC7 */ |
| 167 | {0, 0, 0, 1, 0, 0}, /* PC6 : PC6 */ |
| 168 | {0, 0, 0, 1, 0, 0}, /* PC5 : PC5 */ |
| 169 | {0, 0, 0, 1, 0, 0}, /* PC4 : PC4 */ |
| 170 | {0, 0, 0, 1, 0, 0}, /* PC3 : PC3 */ |
| 171 | {0, 0, 0, 1, 0, 1}, /* PC2 : ENET FDE */ |
| 172 | {0, 0, 0, 1, 0, 0}, /* PC1 : ENET DSQE */ |
| 173 | {0, 0, 0, 1, 0, 0}, /* PC0 : ENET LBK */ |
| 174 | }, |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 175 | |
Wolfgang Grandegger | 9039ce1 | 2008-06-05 13:12:00 +0200 | [diff] [blame] | 176 | /* Port D: conf, ppar, psor, pdir, podr, pdat */ |
| 177 | { |
Wolfgang Grandegger | 3a53fa6 | 2008-06-05 13:12:01 +0200 | [diff] [blame] | 178 | #ifdef CONFIG_TQM8560 |
Wolfgang Grandegger | 9039ce1 | 2008-06-05 13:12:00 +0200 | [diff] [blame] | 179 | {1, 1, 0, 0, 0, 0}, /* PD31: SCC1 EN RxD */ |
| 180 | {1, 1, 1, 1, 0, 0}, /* PD30: SCC1 EN TxD */ |
| 181 | {1, 1, 0, 1, 0, 0}, /* PD29: SCC1 EN TENA */ |
Wolfgang Grandegger | 3a53fa6 | 2008-06-05 13:12:01 +0200 | [diff] [blame] | 182 | #else /* !CONFIG_TQM8560 */ |
| 183 | {0, 0, 0, 0, 0, 0}, /* PD31: PD31 */ |
| 184 | {0, 0, 0, 0, 0, 0}, /* PD30: PD30 */ |
| 185 | {0, 0, 0, 0, 0, 0}, /* PD29: PD29 */ |
| 186 | #endif /* CONFIG_TQM8560 */ |
Wolfgang Grandegger | 9039ce1 | 2008-06-05 13:12:00 +0200 | [diff] [blame] | 187 | {1, 1, 0, 0, 0, 0}, /* PD28: PD28 */ |
| 188 | {1, 1, 0, 1, 0, 0}, /* PD27: PD27 */ |
| 189 | {1, 1, 0, 1, 0, 0}, /* PD26: PD26 */ |
| 190 | {0, 0, 0, 1, 0, 0}, /* PD25: PD25 */ |
| 191 | {0, 0, 0, 1, 0, 0}, /* PD24: PD24 */ |
| 192 | {0, 0, 0, 1, 0, 0}, /* PD23: PD23 */ |
| 193 | {0, 0, 0, 1, 0, 0}, /* PD22: PD22 */ |
| 194 | {0, 0, 0, 1, 0, 0}, /* PD21: PD21 */ |
| 195 | {0, 0, 0, 1, 0, 0}, /* PD20: PD20 */ |
| 196 | {0, 0, 0, 1, 0, 0}, /* PD19: PD19 */ |
| 197 | {0, 0, 0, 1, 0, 0}, /* PD18: PD18 */ |
| 198 | {0, 1, 0, 0, 0, 0}, /* PD17: FCC1 ATMRXPRTY */ |
| 199 | {0, 1, 0, 1, 0, 0}, /* PD16: FCC1 ATMTXPRTY */ |
| 200 | {0, 1, 1, 0, 1, 0}, /* PD15: I2C SDA */ |
| 201 | {0, 0, 0, 1, 0, 0}, /* PD14: LED */ |
| 202 | {0, 0, 0, 0, 0, 0}, /* PD13: PD13 */ |
| 203 | {0, 0, 0, 0, 0, 0}, /* PD12: PD12 */ |
| 204 | {0, 0, 0, 0, 0, 0}, /* PD11: PD11 */ |
| 205 | {0, 0, 0, 0, 0, 0}, /* PD10: PD10 */ |
| 206 | {0, 1, 0, 1, 0, 0}, /* PD9 : SMC1 TXD */ |
| 207 | {0, 1, 0, 0, 0, 0}, /* PD8 : SMC1 RXD */ |
| 208 | {0, 0, 0, 1, 0, 1}, /* PD7 : PD7 */ |
| 209 | {0, 0, 0, 1, 0, 1}, /* PD6 : PD6 */ |
| 210 | {0, 0, 0, 1, 0, 1}, /* PD5 : PD5 */ |
| 211 | {0, 0, 0, 1, 0, 1}, /* PD4 : PD4 */ |
| 212 | {0, 0, 0, 0, 0, 0}, /* PD3 : pin doesn't exist */ |
| 213 | {0, 0, 0, 0, 0, 0}, /* PD2 : pin doesn't exist */ |
| 214 | {0, 0, 0, 0, 0, 0}, /* PD1 : pin doesn't exist */ |
| 215 | {0, 0, 0, 0, 0, 0} /* PD0 : pin doesn't exist */ |
| 216 | } |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 217 | }; |
Stefan Roese | 0955402 | 2005-11-30 13:06:40 +0100 | [diff] [blame] | 218 | #endif /* CONFIG_CPM2 */ |
| 219 | |
| 220 | #define CASL_STRING1 "casl=xx" |
| 221 | #define CASL_STRING2 "casl=" |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 222 | |
Stefan Roese | 0955402 | 2005-11-30 13:06:40 +0100 | [diff] [blame] | 223 | static const int casl_table[] = { 20, 25, 30 }; |
| 224 | #define N_CASL (sizeof(casl_table) / sizeof(casl_table[0])) |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 225 | |
Wolfgang Grandegger | 9039ce1 | 2008-06-05 13:12:00 +0200 | [diff] [blame] | 226 | int cas_latency (void) |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 227 | { |
Wolfgang Grandegger | 9039ce1 | 2008-06-05 13:12:00 +0200 | [diff] [blame] | 228 | char *s = getenv ("serial#"); |
Stefan Roese | 0955402 | 2005-11-30 13:06:40 +0100 | [diff] [blame] | 229 | int casl; |
| 230 | int val; |
| 231 | int i; |
| 232 | |
| 233 | casl = CONFIG_DDR_DEFAULT_CL; |
| 234 | |
| 235 | if (s != NULL) { |
Wolfgang Grandegger | 9039ce1 | 2008-06-05 13:12:00 +0200 | [diff] [blame] | 236 | if (strncmp(s + strlen (s) - strlen (CASL_STRING1), |
| 237 | CASL_STRING2, strlen (CASL_STRING2)) == 0) { |
| 238 | val = simple_strtoul (s + strlen (s) - 2, NULL, 10); |
Stefan Roese | 0955402 | 2005-11-30 13:06:40 +0100 | [diff] [blame] | 239 | |
Wolfgang Grandegger | 9039ce1 | 2008-06-05 13:12:00 +0200 | [diff] [blame] | 240 | for (i = 0; i < N_CASL; ++i) { |
Stefan Roese | 0955402 | 2005-11-30 13:06:40 +0100 | [diff] [blame] | 241 | if (val == casl_table[i]) { |
| 242 | return val; |
| 243 | } |
| 244 | } |
| 245 | } |
| 246 | } |
| 247 | |
| 248 | return casl; |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 249 | } |
| 250 | |
| 251 | int checkboard (void) |
| 252 | { |
Wolfgang Grandegger | 9039ce1 | 2008-06-05 13:12:00 +0200 | [diff] [blame] | 253 | char *s = getenv ("serial#"); |
Stefan Roese | 0955402 | 2005-11-30 13:06:40 +0100 | [diff] [blame] | 254 | |
Wolfgang Grandegger | 9039ce1 | 2008-06-05 13:12:00 +0200 | [diff] [blame] | 255 | printf ("Board: %s", CONFIG_BOARDNAME); |
Stefan Roese | 0955402 | 2005-11-30 13:06:40 +0100 | [diff] [blame] | 256 | if (s != NULL) { |
Wolfgang Grandegger | 9039ce1 | 2008-06-05 13:12:00 +0200 | [diff] [blame] | 257 | puts (", serial# "); |
| 258 | puts (s); |
Stefan Roese | 0955402 | 2005-11-30 13:06:40 +0100 | [diff] [blame] | 259 | } |
Wolfgang Grandegger | 9039ce1 | 2008-06-05 13:12:00 +0200 | [diff] [blame] | 260 | putc ('\n'); |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 261 | |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 262 | /* |
| 263 | * Initialize local bus. |
| 264 | */ |
| 265 | local_bus_init (); |
| 266 | |
| 267 | return 0; |
| 268 | } |
| 269 | |
Stefan Roese | 0955402 | 2005-11-30 13:06:40 +0100 | [diff] [blame] | 270 | int misc_init_r (void) |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 271 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 272 | volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 273 | |
Stefan Roese | 0955402 | 2005-11-30 13:06:40 +0100 | [diff] [blame] | 274 | /* |
| 275 | * Adjust flash start and offset to detected values |
| 276 | */ |
| 277 | gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; |
| 278 | gd->bd->bi_flashoffset = 0; |
Stefan Roese | ac55328 | 2005-08-31 12:55:50 +0200 | [diff] [blame] | 279 | |
Stefan Roese | 0955402 | 2005-11-30 13:06:40 +0100 | [diff] [blame] | 280 | /* |
Wolfgang Grandegger | fe18884 | 2008-06-05 13:12:03 +0200 | [diff] [blame] | 281 | * Recalculate CS configuration if second FLASH bank is available |
Stefan Roese | 0955402 | 2005-11-30 13:06:40 +0100 | [diff] [blame] | 282 | */ |
Wolfgang Grandegger | fe18884 | 2008-06-05 13:12:03 +0200 | [diff] [blame] | 283 | if (flash_info[0].size > 0) { |
| 284 | memctl->or1 = ((-flash_info[0].size) & 0xffff8000) | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 285 | (CONFIG_SYS_OR1_PRELIM & 0x00007fff); |
Wolfgang Grandegger | fe18884 | 2008-06-05 13:12:03 +0200 | [diff] [blame] | 286 | memctl->br1 = gd->bd->bi_flashstart | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 287 | (CONFIG_SYS_BR1_PRELIM & 0x00007fff); |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 288 | /* |
Wolfgang Grandegger | fe18884 | 2008-06-05 13:12:03 +0200 | [diff] [blame] | 289 | * Re-check to get correct base address for bank 1 |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 290 | */ |
Wolfgang Grandegger | fe18884 | 2008-06-05 13:12:03 +0200 | [diff] [blame] | 291 | flash_get_size (gd->bd->bi_flashstart, 0); |
| 292 | } else { |
| 293 | memctl->or1 = 0; |
| 294 | memctl->br1 = 0; |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 295 | } |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 296 | |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 297 | /* |
Wolfgang Grandegger | fe18884 | 2008-06-05 13:12:03 +0200 | [diff] [blame] | 298 | * If bank 1 is equipped, bank 0 is mapped after bank 1 |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 299 | */ |
Wolfgang Grandegger | fe18884 | 2008-06-05 13:12:03 +0200 | [diff] [blame] | 300 | memctl->or0 = ((-flash_info[1].size) & 0xffff8000) | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 301 | (CONFIG_SYS_OR0_PRELIM & 0x00007fff); |
Wolfgang Grandegger | fe18884 | 2008-06-05 13:12:03 +0200 | [diff] [blame] | 302 | memctl->br0 = (gd->bd->bi_flashstart + flash_info[0].size) | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 303 | (CONFIG_SYS_BR0_PRELIM & 0x00007fff); |
Wolfgang Grandegger | fe18884 | 2008-06-05 13:12:03 +0200 | [diff] [blame] | 304 | /* |
| 305 | * Re-check to get correct base address for bank 0 |
| 306 | */ |
| 307 | flash_get_size (gd->bd->bi_flashstart + flash_info[0].size, 1); |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 308 | |
Wolfgang Grandegger | fe18884 | 2008-06-05 13:12:03 +0200 | [diff] [blame] | 309 | /* |
| 310 | * Re-do flash protection upon new addresses |
| 311 | */ |
| 312 | flash_protect (FLAG_PROTECT_CLEAR, |
| 313 | gd->bd->bi_flashstart, 0xffffffff, |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 314 | &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 315 | |
Wolfgang Grandegger | fe18884 | 2008-06-05 13:12:03 +0200 | [diff] [blame] | 316 | /* Monitor protection ON by default */ |
| 317 | flash_protect (FLAG_PROTECT_SET, |
Wolfgang Grandegger | 4988451 | 2009-02-11 18:38:19 +0100 | [diff] [blame] | 318 | CONFIG_SYS_MONITOR_BASE, 0xffffffff, |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 319 | &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); |
Stefan Roese | 0955402 | 2005-11-30 13:06:40 +0100 | [diff] [blame] | 320 | |
Wolfgang Grandegger | fe18884 | 2008-06-05 13:12:03 +0200 | [diff] [blame] | 321 | /* Environment protection ON by default */ |
| 322 | flash_protect (FLAG_PROTECT_SET, |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 323 | CONFIG_ENV_ADDR, |
| 324 | CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 325 | &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); |
Stefan Roese | 0955402 | 2005-11-30 13:06:40 +0100 | [diff] [blame] | 326 | |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 327 | #ifdef CONFIG_ENV_ADDR_REDUND |
Wolfgang Grandegger | fe18884 | 2008-06-05 13:12:03 +0200 | [diff] [blame] | 328 | /* Redundant environment protection ON by default */ |
| 329 | flash_protect (FLAG_PROTECT_SET, |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 330 | CONFIG_ENV_ADDR_REDUND, |
Wolfgang Denk | 4791383 | 2009-05-15 00:16:03 +0200 | [diff] [blame] | 331 | CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 332 | &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); |
Wolfgang Grandegger | fe18884 | 2008-06-05 13:12:03 +0200 | [diff] [blame] | 333 | #endif |
Stefan Roese | 0955402 | 2005-11-30 13:06:40 +0100 | [diff] [blame] | 334 | |
| 335 | return 0; |
| 336 | } |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 337 | |
Wolfgang Grandegger | c5809d7 | 2008-06-05 13:12:05 +0200 | [diff] [blame] | 338 | #ifdef CONFIG_CAN_DRIVER |
| 339 | /* |
| 340 | * Initialize UPMC RAM |
| 341 | */ |
| 342 | static void upmc_write (u_char addr, uint val) |
| 343 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 344 | volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); |
Wolfgang Grandegger | c5809d7 | 2008-06-05 13:12:05 +0200 | [diff] [blame] | 345 | |
| 346 | out_be32 (&lbc->mdr, val); |
| 347 | |
| 348 | clrsetbits_be32(&lbc->mcmr, MxMR_MAD_MSK, |
| 349 | MxMR_OP_WARR | (addr & MxMR_MAD_MSK)); |
| 350 | |
| 351 | /* dummy access to perform write */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 352 | out_8 ((void __iomem *)CONFIG_SYS_CAN_BASE, 0); |
Wolfgang Grandegger | c5809d7 | 2008-06-05 13:12:05 +0200 | [diff] [blame] | 353 | |
| 354 | /* normal operation */ |
| 355 | clrbits_be32(&lbc->mcmr, MxMR_OP_WARR); |
| 356 | } |
| 357 | #endif /* CONFIG_CAN_DRIVER */ |
| 358 | |
Wolfgang Grandegger | 328c6ec | 2008-06-05 13:12:07 +0200 | [diff] [blame] | 359 | uint get_lbc_clock (void) |
| 360 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 361 | volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); |
Wolfgang Grandegger | 328c6ec | 2008-06-05 13:12:07 +0200 | [diff] [blame] | 362 | sys_info_t sys_info; |
Trent Piepho | 1b560ac | 2008-12-03 15:16:34 -0800 | [diff] [blame] | 363 | ulong clkdiv = lbc->lcrr & LCRR_CLKDIV; |
Wolfgang Grandegger | 328c6ec | 2008-06-05 13:12:07 +0200 | [diff] [blame] | 364 | |
| 365 | get_sys_info (&sys_info); |
| 366 | |
| 367 | if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { |
| 368 | #ifdef CONFIG_MPC8548 |
| 369 | /* |
| 370 | * Yes, the entire PQ38 family use the same |
| 371 | * bit-representation for twice the clock divider value. |
| 372 | */ |
| 373 | clkdiv *= 2; |
| 374 | #endif |
| 375 | return sys_info.freqSystemBus / clkdiv; |
| 376 | } |
| 377 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 378 | puts("Invalid clock divider value in CONFIG_SYS_LBC_LCRR\n"); |
Wolfgang Grandegger | 328c6ec | 2008-06-05 13:12:07 +0200 | [diff] [blame] | 379 | |
| 380 | return 0; |
| 381 | } |
| 382 | |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 383 | /* |
| 384 | * Initialize Local Bus |
| 385 | */ |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 386 | void local_bus_init (void) |
| 387 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 388 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
| 389 | volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); |
Wolfgang Grandegger | 328c6ec | 2008-06-05 13:12:07 +0200 | [diff] [blame] | 390 | uint lbc_mhz = get_lbc_clock () / 1000000; |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 391 | |
Wolfgang Grandegger | 328c6ec | 2008-06-05 13:12:07 +0200 | [diff] [blame] | 392 | #ifdef CONFIG_MPC8548 |
| 393 | uint svr = get_svr (); |
| 394 | uint lcrr; |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 395 | |
| 396 | /* |
Wolfgang Grandegger | 328c6ec | 2008-06-05 13:12:07 +0200 | [diff] [blame] | 397 | * MPC revision < 2.0 |
| 398 | * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU1: |
| 399 | * Modify engineering use only register at address 0xE_0F20. |
| 400 | * "1. Read register at offset 0xE_0F20 |
| 401 | * 2. And value with 0x0000_FFFF |
| 402 | * 3. OR result with 0x0000_0004 |
| 403 | * 4. Write result back to offset 0xE_0F20." |
| 404 | * |
| 405 | * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU2: |
| 406 | * Modify engineering use only register at address 0xE_0F20. |
| 407 | * "1. Read register at offset 0xE_0F20 |
| 408 | * 2. And value with 0xFFFF_FFDF |
| 409 | * 3. Write result back to offset 0xE_0F20." |
| 410 | * |
| 411 | * Since it is the same register, we do the modification in one step. |
| 412 | */ |
| 413 | if (SVR_MAJ (svr) < 2) { |
| 414 | uint dummy = gur->lbiuiplldcr1; |
| 415 | dummy &= 0x0000FFDF; |
| 416 | dummy |= 0x00000004; |
| 417 | gur->lbiuiplldcr1 = dummy; |
| 418 | } |
| 419 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 420 | lcrr = CONFIG_SYS_LBC_LCRR; |
Wolfgang Grandegger | 328c6ec | 2008-06-05 13:12:07 +0200 | [diff] [blame] | 421 | |
| 422 | /* |
| 423 | * Local Bus Clock > 83.3 MHz. According to timing |
| 424 | * specifications set LCRR[EADC] to 2 delay cycles. |
| 425 | */ |
| 426 | if (lbc_mhz > 83) { |
| 427 | lcrr &= ~LCRR_EADC; |
| 428 | lcrr |= LCRR_EADC_2; |
| 429 | } |
| 430 | |
| 431 | /* |
| 432 | * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30 |
| 433 | * disable PLL bypass for Local Bus Clock > 83 MHz. |
| 434 | */ |
| 435 | if (lbc_mhz >= 66) |
| 436 | lcrr &= (~LCRR_DBYP); /* DLL Enabled */ |
| 437 | |
| 438 | else |
| 439 | lcrr |= LCRR_DBYP; /* DLL Bypass */ |
| 440 | |
| 441 | lbc->lcrr = lcrr; |
| 442 | asm ("sync;isync;msync"); |
| 443 | |
| 444 | /* |
| 445 | * According to MPC8548ERMAD Rev.1.3 read back LCRR |
| 446 | * and terminate with isync |
| 447 | */ |
| 448 | lcrr = lbc->lcrr; |
| 449 | asm ("isync;"); |
| 450 | |
| 451 | /* let DLL stabilize */ |
| 452 | udelay (500); |
| 453 | |
| 454 | #else /* !CONFIG_MPC8548 */ |
| 455 | |
| 456 | /* |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 457 | * Errata LBC11. |
| 458 | * Fix Local Bus clock glitch when DLL is enabled. |
| 459 | * |
Wolfgang Denk | af0501a | 2008-10-19 02:35:50 +0200 | [diff] [blame] | 460 | * If localbus freq is < 66MHz, DLL bypass mode must be used. |
| 461 | * If localbus freq is > 133MHz, DLL can be safely enabled. |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 462 | * Between 66 and 133, the DLL is enabled with an override workaround. |
| 463 | */ |
| 464 | |
Wolfgang Grandegger | 328c6ec | 2008-06-05 13:12:07 +0200 | [diff] [blame] | 465 | if (lbc_mhz < 66) { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 466 | lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */ |
Stefan Roese | 3762825 | 2008-08-06 14:05:38 +0200 | [diff] [blame] | 467 | lbc->ltedr = LTEDR_BMD | LTEDR_PARD | LTEDR_WPD | LTEDR_WARA | |
| 468 | LTEDR_RAWA | LTEDR_CSD; /* Disable all error checking */ |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 469 | |
Wolfgang Grandegger | 328c6ec | 2008-06-05 13:12:07 +0200 | [diff] [blame] | 470 | } else if (lbc_mhz >= 133) { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 471 | lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 472 | |
| 473 | } else { |
| 474 | /* |
| 475 | * On REV1 boards, need to change CLKDIV before enable DLL. |
| 476 | * Default CLKDIV is 8, change it to 4 temporarily. |
| 477 | */ |
| 478 | uint pvr = get_pvr (); |
| 479 | uint temp_lbcdll = 0; |
| 480 | |
| 481 | if (pvr == PVR_85xx_REV1) { |
| 482 | /* FIXME: Justify the high bit here. */ |
| 483 | lbc->lcrr = 0x10000004; |
| 484 | } |
| 485 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 486 | lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 487 | udelay (200); |
| 488 | |
| 489 | /* |
| 490 | * Sample LBC DLL ctrl reg, upshift it to set the |
| 491 | * override bits. |
| 492 | */ |
| 493 | temp_lbcdll = gur->lbcdllcr; |
| 494 | gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); |
| 495 | asm ("sync;isync;msync"); |
| 496 | } |
Wolfgang Grandegger | 328c6ec | 2008-06-05 13:12:07 +0200 | [diff] [blame] | 497 | #endif /* !CONFIG_MPC8548 */ |
Wolfgang Grandegger | c5809d7 | 2008-06-05 13:12:05 +0200 | [diff] [blame] | 498 | |
| 499 | #ifdef CONFIG_CAN_DRIVER |
| 500 | /* |
| 501 | * According to timing specifications EAD must be |
| 502 | * set if Local Bus Clock is > 83 MHz. |
| 503 | */ |
Wolfgang Grandegger | 328c6ec | 2008-06-05 13:12:07 +0200 | [diff] [blame] | 504 | if (lbc_mhz > 83) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 505 | out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD); |
Wolfgang Grandegger | c5809d7 | 2008-06-05 13:12:05 +0200 | [diff] [blame] | 506 | else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 507 | out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN); |
| 508 | out_be32 (&lbc->br2, CONFIG_SYS_BR2_CAN); |
Wolfgang Grandegger | c5809d7 | 2008-06-05 13:12:05 +0200 | [diff] [blame] | 509 | |
| 510 | /* LGPL4 is UPWAIT */ |
| 511 | out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X); |
| 512 | |
| 513 | /* Initialize UPMC for CAN: single read */ |
| 514 | upmc_write (0x00, 0xFFFFED00); |
| 515 | upmc_write (0x01, 0xCCFFCC00); |
| 516 | upmc_write (0x02, 0x00FFCF00); |
| 517 | upmc_write (0x03, 0x00FFCF00); |
| 518 | upmc_write (0x04, 0x00FFDC00); |
| 519 | upmc_write (0x05, 0x00FFCF00); |
| 520 | upmc_write (0x06, 0x00FFED00); |
| 521 | upmc_write (0x07, 0x3FFFCC07); |
| 522 | |
| 523 | /* Initialize UPMC for CAN: single write */ |
| 524 | upmc_write (0x18, 0xFFFFED00); |
| 525 | upmc_write (0x19, 0xCCFFEC00); |
| 526 | upmc_write (0x1A, 0x00FFED80); |
| 527 | upmc_write (0x1B, 0x00FFED80); |
| 528 | upmc_write (0x1C, 0x00FFFC00); |
| 529 | upmc_write (0x1D, 0x0FFFEC00); |
| 530 | upmc_write (0x1E, 0x0FFFEF00); |
| 531 | upmc_write (0x1F, 0x3FFFEC05); |
| 532 | #endif /* CONFIG_CAN_DRIVER */ |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 533 | } |
| 534 | |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 535 | /* |
| 536 | * Initialize PCI Devices, report devices found. |
| 537 | */ |
Wolfgang Grandegger | 8754a97 | 2008-06-05 13:12:08 +0200 | [diff] [blame] | 538 | static int first_free_busno; |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 539 | |
Wolfgang Grandegger | b9864be | 2009-02-11 18:38:20 +0100 | [diff] [blame] | 540 | #ifdef CONFIG_PCI1 |
Wolfgang Grandegger | 8754a97 | 2008-06-05 13:12:08 +0200 | [diff] [blame] | 541 | static struct pci_controller pci1_hose; |
Wolfgang Grandegger | b9864be | 2009-02-11 18:38:20 +0100 | [diff] [blame] | 542 | #endif /* CONFIG_PCI1 */ |
Wolfgang Grandegger | 8754a97 | 2008-06-05 13:12:08 +0200 | [diff] [blame] | 543 | |
| 544 | #ifdef CONFIG_PCIE1 |
| 545 | static struct pci_controller pcie1_hose; |
| 546 | #endif /* CONFIG_PCIE1 */ |
| 547 | |
| 548 | static inline void init_pci1(void) |
| 549 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 550 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
Wolfgang Grandegger | b9864be | 2009-02-11 18:38:20 +0100 | [diff] [blame] | 551 | #ifdef CONFIG_PCI1 |
Wolfgang Grandegger | 8754a97 | 2008-06-05 13:12:08 +0200 | [diff] [blame] | 552 | uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 553 | volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCI1_ADDR; |
Wolfgang Grandegger | 8754a97 | 2008-06-05 13:12:08 +0200 | [diff] [blame] | 554 | struct pci_controller *hose = &pci1_hose; |
Kumar Gala | c10a0c4 | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 555 | struct pci_region *r = hose->regions; |
Wolfgang Grandegger | 8754a97 | 2008-06-05 13:12:08 +0200 | [diff] [blame] | 556 | |
| 557 | /* PORDEVSR[15] */ |
| 558 | uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; |
| 559 | /* PORDEVSR[14] */ |
| 560 | uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; |
| 561 | /* PORPLLSR[16] */ |
| 562 | uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; |
| 563 | |
| 564 | uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || |
| 565 | (host_agent == 6); |
| 566 | |
| 567 | uint pci_speed = CONFIG_SYS_CLK_FREQ; /* PCI PSPEED in [4:5] */ |
| 568 | |
| 569 | if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { |
| 570 | printf ("PCI1: %d bit, %s MHz, %s, %s, %s\n", |
| 571 | (pci_32) ? 32 : 64, |
| 572 | (pci_speed == 33333333) ? "33" : |
| 573 | (pci_speed == 66666666) ? "66" : "unknown", |
| 574 | pci_clk_sel ? "sync" : "async", |
| 575 | pci_agent ? "agent" : "host", |
| 576 | pci_arb ? "arbiter" : "external-arbiter"); |
| 577 | |
Wolfgang Grandegger | 8754a97 | 2008-06-05 13:12:08 +0200 | [diff] [blame] | 578 | /* outbound memory */ |
Kumar Gala | c10a0c4 | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 579 | pci_set_region (r++, |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 580 | CONFIG_SYS_PCI1_MEM_BASE, |
| 581 | CONFIG_SYS_PCI1_MEM_PHYS, |
| 582 | CONFIG_SYS_PCI1_MEM_SIZE, |
Wolfgang Grandegger | 8754a97 | 2008-06-05 13:12:08 +0200 | [diff] [blame] | 583 | PCI_REGION_MEM); |
| 584 | |
| 585 | /* outbound io */ |
Kumar Gala | c10a0c4 | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 586 | pci_set_region (r++, |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 587 | CONFIG_SYS_PCI1_IO_BASE, |
| 588 | CONFIG_SYS_PCI1_IO_PHYS, |
| 589 | CONFIG_SYS_PCI1_IO_SIZE, |
Wolfgang Grandegger | 8754a97 | 2008-06-05 13:12:08 +0200 | [diff] [blame] | 590 | PCI_REGION_IO); |
| 591 | |
Kumar Gala | c10a0c4 | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 592 | hose->region_count = r - hose->regions; |
Wolfgang Grandegger | 8754a97 | 2008-06-05 13:12:08 +0200 | [diff] [blame] | 593 | |
| 594 | hose->first_busno = first_free_busno; |
Wolfgang Grandegger | 8754a97 | 2008-06-05 13:12:08 +0200 | [diff] [blame] | 595 | |
Kumar Gala | 65e198d | 2009-08-03 20:44:55 -0500 | [diff] [blame] | 596 | fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); |
Wolfgang Grandegger | 8754a97 | 2008-06-05 13:12:08 +0200 | [diff] [blame] | 597 | |
| 598 | printf (" PCI on bus %02x..%02x\n", |
| 599 | hose->first_busno, hose->last_busno); |
| 600 | |
| 601 | first_free_busno = hose->last_busno + 1; |
| 602 | #ifdef CONFIG_PCIX_CHECK |
Peter Tyser | af7c3e3 | 2008-12-01 13:47:12 -0600 | [diff] [blame] | 603 | if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) { |
Wolfgang Grandegger | 8754a97 | 2008-06-05 13:12:08 +0200 | [diff] [blame] | 604 | ushort reg16 = |
| 605 | PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ | |
| 606 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; |
| 607 | uint dev = PCI_BDF(hose->first_busno, 0, 0); |
| 608 | |
| 609 | /* PCI-X init */ |
| 610 | if (CONFIG_SYS_CLK_FREQ < 66000000) |
| 611 | puts ("PCI-X will only work at 66 MHz\n"); |
| 612 | |
| 613 | pci_hose_write_config_word (hose, dev, PCIX_COMMAND, |
| 614 | reg16); |
| 615 | } |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 616 | #endif |
Wolfgang Grandegger | 8754a97 | 2008-06-05 13:12:08 +0200 | [diff] [blame] | 617 | } else { |
| 618 | puts ("PCI1: disabled\n"); |
| 619 | } |
Wolfgang Grandegger | b9864be | 2009-02-11 18:38:20 +0100 | [diff] [blame] | 620 | #else /* !CONFIG_PCI1 */ |
Wolfgang Grandegger | 8754a97 | 2008-06-05 13:12:08 +0200 | [diff] [blame] | 621 | gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ |
Wolfgang Grandegger | b9864be | 2009-02-11 18:38:20 +0100 | [diff] [blame] | 622 | #endif /* CONFIG_PCI1 */ |
Wolfgang Grandegger | 8754a97 | 2008-06-05 13:12:08 +0200 | [diff] [blame] | 623 | } |
| 624 | |
| 625 | static inline void init_pcie1(void) |
| 626 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 627 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
Wolfgang Grandegger | 8754a97 | 2008-06-05 13:12:08 +0200 | [diff] [blame] | 628 | #ifdef CONFIG_PCIE1 |
| 629 | uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; |
| 630 | uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 631 | volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCIE1_ADDR; |
Wolfgang Grandegger | 8754a97 | 2008-06-05 13:12:08 +0200 | [diff] [blame] | 632 | struct pci_controller *hose = &pcie1_hose; |
| 633 | int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || |
| 634 | (host_agent == 3); |
Kumar Gala | c10a0c4 | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 635 | struct pci_region *r = hose->regions; |
Wolfgang Grandegger | 8754a97 | 2008-06-05 13:12:08 +0200 | [diff] [blame] | 636 | |
| 637 | int pcie_configured = io_sel >= 1; |
| 638 | |
| 639 | if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ |
| 640 | printf ("PCIe: %s, base address %x", |
| 641 | pcie_ep ? "End point" : "Root complex", (uint)pci); |
| 642 | |
| 643 | if (pci->pme_msg_det) { |
| 644 | pci->pme_msg_det = 0xffffffff; |
| 645 | debug (", with errors. Clearing. Now 0x%08x", |
| 646 | pci->pme_msg_det); |
| 647 | } |
| 648 | puts ("\n"); |
| 649 | |
Wolfgang Grandegger | 8754a97 | 2008-06-05 13:12:08 +0200 | [diff] [blame] | 650 | /* outbound memory */ |
Kumar Gala | c10a0c4 | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 651 | pci_set_region (r++, |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 652 | CONFIG_SYS_PCIE1_MEM_BASE, |
| 653 | CONFIG_SYS_PCIE1_MEM_PHYS, |
| 654 | CONFIG_SYS_PCIE1_MEM_SIZE, |
Wolfgang Grandegger | 8754a97 | 2008-06-05 13:12:08 +0200 | [diff] [blame] | 655 | PCI_REGION_MEM); |
| 656 | |
| 657 | /* outbound io */ |
Kumar Gala | c10a0c4 | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 658 | pci_set_region (r++, |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 659 | CONFIG_SYS_PCIE1_IO_BASE, |
| 660 | CONFIG_SYS_PCIE1_IO_PHYS, |
| 661 | CONFIG_SYS_PCIE1_IO_SIZE, |
Wolfgang Grandegger | 8754a97 | 2008-06-05 13:12:08 +0200 | [diff] [blame] | 662 | PCI_REGION_IO); |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 663 | |
Kumar Gala | c10a0c4 | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 664 | hose->region_count = r - hose->regions; |
Wolfgang Grandegger | 8754a97 | 2008-06-05 13:12:08 +0200 | [diff] [blame] | 665 | |
| 666 | hose->first_busno = first_free_busno; |
Wolfgang Grandegger | 8754a97 | 2008-06-05 13:12:08 +0200 | [diff] [blame] | 667 | |
Kumar Gala | 65e198d | 2009-08-03 20:44:55 -0500 | [diff] [blame] | 668 | fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); |
Wolfgang Grandegger | 8754a97 | 2008-06-05 13:12:08 +0200 | [diff] [blame] | 669 | printf (" PCIe on bus %02x..%02x\n", |
| 670 | hose->first_busno, hose->last_busno); |
| 671 | |
| 672 | first_free_busno = hose->last_busno + 1; |
| 673 | |
| 674 | } else { |
| 675 | printf ("PCIe: disabled\n"); |
| 676 | } |
| 677 | #else /* !CONFIG_PCIE1 */ |
| 678 | gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ |
| 679 | #endif /* CONFIG_PCIE1 */ |
| 680 | } |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 681 | |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 682 | void pci_init_board (void) |
| 683 | { |
Wolfgang Grandegger | 8754a97 | 2008-06-05 13:12:08 +0200 | [diff] [blame] | 684 | init_pci1(); |
| 685 | init_pcie1(); |
wdenk | 8e5263c | 2005-04-05 16:26:47 +0000 | [diff] [blame] | 686 | } |
Wolfgang Denk | 1216885 | 2006-06-16 16:40:54 +0200 | [diff] [blame] | 687 | |
Wolfgang Grandegger | 8754a97 | 2008-06-05 13:12:08 +0200 | [diff] [blame] | 688 | #ifdef CONFIG_OF_BOARD_SETUP |
Wolfgang Grandegger | f5be52d | 2008-06-05 13:12:06 +0200 | [diff] [blame] | 689 | void ft_board_setup (void *blob, bd_t *bd) |
| 690 | { |
Wolfgang Grandegger | f5be52d | 2008-06-05 13:12:06 +0200 | [diff] [blame] | 691 | ft_cpu_setup (blob, bd); |
| 692 | |
Wolfgang Grandegger | b9864be | 2009-02-11 18:38:20 +0100 | [diff] [blame] | 693 | #ifdef CONFIG_PCI1 |
Kumar Gala | c10a0c4 | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 694 | ft_fsl_pci_setup(blob, "pci0", &pci1_hose); |
| 695 | #endif |
Wolfgang Grandegger | 8754a97 | 2008-06-05 13:12:08 +0200 | [diff] [blame] | 696 | #ifdef CONFIG_PCIE1 |
Kumar Gala | c10a0c4 | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 697 | ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); |
| 698 | #endif |
Wolfgang Grandegger | f5be52d | 2008-06-05 13:12:06 +0200 | [diff] [blame] | 699 | } |
Wolfgang Grandegger | 8754a97 | 2008-06-05 13:12:08 +0200 | [diff] [blame] | 700 | #endif /* CONFIG_OF_BOARD_SETUP */ |
Wolfgang Grandegger | f5be52d | 2008-06-05 13:12:06 +0200 | [diff] [blame] | 701 | |
Wolfgang Denk | 1216885 | 2006-06-16 16:40:54 +0200 | [diff] [blame] | 702 | #ifdef CONFIG_BOARD_EARLY_INIT_R |
| 703 | int board_early_init_r (void) |
| 704 | { |
| 705 | #ifdef CONFIG_PS2MULT |
Wolfgang Grandegger | 9039ce1 | 2008-06-05 13:12:00 +0200 | [diff] [blame] | 706 | ps2mult_early_init (); |
Wolfgang Denk | 1216885 | 2006-06-16 16:40:54 +0200 | [diff] [blame] | 707 | #endif /* CONFIG_PS2MULT */ |
| 708 | return (0); |
| 709 | } |
| 710 | #endif /* CONFIG_BOARD_EARLY_INIT_R */ |
Ben Warren | 052a5ea | 2008-08-31 20:37:00 -0700 | [diff] [blame] | 711 | |
| 712 | int board_eth_init(bd_t *bis) |
| 713 | { |
| 714 | cpu_eth_init(bis); /* Intialize TSECs first */ |
| 715 | return pci_eth_init(bis); |
| 716 | } |