| Marcel Ziswiler | 64e36c1 | 2022-07-21 15:27:30 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 OR MIT |
| 2 | // |
| 3 | // Copyright 2019 Armadeus Systems <support@armadeus.com> |
| 4 | |
| 5 | / { |
| 6 | memory@80000000 { |
| 7 | device_type = "memory"; |
| 8 | reg = <0x80000000 0>; /* will be filled by U-Boot */ |
| 9 | }; |
| 10 | |
| 11 | reg_3v3: regulator-3v3 { |
| 12 | compatible = "regulator-fixed"; |
| 13 | regulator-name = "3V3"; |
| 14 | regulator-min-microvolt = <3300000>; |
| 15 | regulator-max-microvolt = <3300000>; |
| 16 | }; |
| 17 | |
| 18 | usdhc3_pwrseq: usdhc3-pwrseq { |
| 19 | compatible = "mmc-pwrseq-simple"; |
| 20 | reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; |
| 21 | }; |
| 22 | }; |
| 23 | |
| 24 | &fec1 { |
| 25 | pinctrl-names = "default"; |
| 26 | pinctrl-0 = <&pinctrl_enet1>; |
| 27 | phy-mode = "rmii"; |
| 28 | phy-reset-duration = <1>; |
| 29 | phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; |
| 30 | phy-handle = <ðphy1>; |
| 31 | phy-supply = <®_3v3>; |
| 32 | status = "okay"; |
| 33 | |
| 34 | mdio: mdio { |
| 35 | #address-cells = <1>; |
| 36 | #size-cells = <0>; |
| 37 | |
| 38 | ethphy1: ethernet-phy@1 { |
| 39 | compatible = "ethernet-phy-ieee802.3-c22"; |
| 40 | reg = <1>; |
| 41 | interrupt-parent = <&gpio4>; |
| 42 | interrupts = <16 IRQ_TYPE_LEVEL_LOW>; |
| 43 | status = "okay"; |
| 44 | }; |
| 45 | }; |
| 46 | }; |
| 47 | |
| 48 | /* Bluetooth */ |
| 49 | &uart8 { |
| 50 | pinctrl-names = "default"; |
| 51 | pinctrl-0 = <&pinctrl_uart8>; |
| 52 | uart-has-rtscts; |
| 53 | status = "okay"; |
| 54 | }; |
| 55 | |
| 56 | /* eMMC */ |
| 57 | &usdhc1 { |
| 58 | pinctrl-names = "default"; |
| 59 | pinctrl-0 = <&pinctrl_usdhc1>; |
| 60 | bus-width = <8>; |
| 61 | no-1-8-v; |
| 62 | non-removable; |
| 63 | status = "okay"; |
| 64 | }; |
| 65 | |
| 66 | /* WiFi */ |
| 67 | &usdhc2 { |
| 68 | pinctrl-names = "default"; |
| 69 | pinctrl-0 = <&pinctrl_usdhc2>; |
| 70 | bus-width = <4>; |
| 71 | no-1-8-v; |
| 72 | non-removable; |
| 73 | mmc-pwrseq = <&usdhc3_pwrseq>; |
| 74 | status = "okay"; |
| 75 | |
| 76 | #address-cells = <1>; |
| 77 | #size-cells = <0>; |
| 78 | |
| 79 | brcmf: wifi@1 { |
| 80 | compatible = "brcm,bcm4329-fmac"; |
| 81 | reg = <1>; |
| 82 | interrupt-parent = <&gpio2>; |
| 83 | interrupts = <8 IRQ_TYPE_LEVEL_LOW>; |
| 84 | interrupt-names = "host-wake"; |
| 85 | }; |
| 86 | }; |
| 87 | |
| 88 | &iomuxc { |
| 89 | pinctrl_enet1: enet1grp { |
| 90 | fsl,pins = < |
| 91 | MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 |
| 92 | MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 |
| 93 | MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x130b0 |
| 94 | MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x130b0 |
| 95 | MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x130b0 |
| 96 | MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x130b0 |
| 97 | MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 |
| 98 | MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 |
| 99 | MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 |
| 100 | /* INT# */ |
| 101 | MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x1b0b0 |
| 102 | /* RST# */ |
| 103 | MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x130b0 |
| 104 | MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 |
| 105 | >; |
| 106 | }; |
| 107 | |
| 108 | pinctrl_uart8: uart8grp { |
| 109 | fsl,pins = < |
| 110 | MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x1b0b0 |
| 111 | MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x1b0b0 |
| 112 | MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x1b0b0 |
| 113 | MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x1b0b0 |
| 114 | /* BT_REG_ON */ |
| 115 | MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x130b0 |
| 116 | >; |
| 117 | }; |
| 118 | |
| 119 | pinctrl_usdhc1: usdhc1grp { |
| 120 | fsl,pins = < |
| 121 | MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 |
| 122 | MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 |
| 123 | MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 |
| 124 | MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 |
| 125 | MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 |
| 126 | MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 |
| 127 | MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059 |
| 128 | MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059 |
| 129 | MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059 |
| 130 | MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059 |
| 131 | >; |
| 132 | }; |
| 133 | |
| 134 | pinctrl_usdhc2: usdhc2grp { |
| 135 | fsl,pins = < |
| 136 | MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x1b0b0 |
| 137 | MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x100b0 |
| 138 | MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x1b0b0 |
| 139 | MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x1b0b0 |
| 140 | MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x1b0b0 |
| 141 | MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x1b0b0 |
| 142 | /* WL_REG_ON */ |
| 143 | MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x130b0 |
| 144 | /* WL_IRQ */ |
| 145 | MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0 |
| 146 | >; |
| 147 | }; |
| 148 | }; |