Stefan Roese | e463bf3 | 2015-01-19 11:33:42 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2014 Stefan Roese <sr@denx.de> |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <spl.h> |
| 9 | #include <asm/io.h> |
| 10 | #include <asm/arch/cpu.h> |
| 11 | #include <asm/arch/soc.h> |
| 12 | |
| 13 | DECLARE_GLOBAL_DATA_PTR; |
| 14 | |
| 15 | u32 spl_boot_device(void) |
| 16 | { |
Stefan Roese | 6396213 | 2015-07-20 11:20:36 +0200 | [diff] [blame] | 17 | #if defined(CONFIG_SPL_SPI_FLASH_SUPPORT) |
Stefan Roese | e463bf3 | 2015-01-19 11:33:42 +0100 | [diff] [blame] | 18 | return BOOT_DEVICE_SPI; |
Stefan Roese | 6396213 | 2015-07-20 11:20:36 +0200 | [diff] [blame] | 19 | #endif |
| 20 | #if defined(CONFIG_SPL_MMC_SUPPORT) |
| 21 | return BOOT_DEVICE_MMC1; |
| 22 | #endif |
| 23 | } |
| 24 | |
| 25 | #ifdef CONFIG_SPL_MMC_SUPPORT |
| 26 | u32 spl_boot_mode(void) |
| 27 | { |
| 28 | return MMCSD_MODE_RAW; |
Stefan Roese | e463bf3 | 2015-01-19 11:33:42 +0100 | [diff] [blame] | 29 | } |
Stefan Roese | 6396213 | 2015-07-20 11:20:36 +0200 | [diff] [blame] | 30 | #endif |
Stefan Roese | e463bf3 | 2015-01-19 11:33:42 +0100 | [diff] [blame] | 31 | |
| 32 | void board_init_f(ulong dummy) |
| 33 | { |
| 34 | /* Set global data pointer */ |
| 35 | gd = &gdata; |
| 36 | |
| 37 | /* Linux expects the internal registers to be at 0xf1000000 */ |
| 38 | arch_cpu_init(); |
| 39 | |
Stefan Roese | d7f2c12 | 2015-04-17 18:13:06 +0200 | [diff] [blame] | 40 | /* |
| 41 | * Pin muxing needs to be done before UART output, since |
| 42 | * on A38x the UART pins need some re-muxing for output |
| 43 | * to work. |
| 44 | */ |
| 45 | board_early_init_f(); |
| 46 | |
Stefan Roese | e463bf3 | 2015-01-19 11:33:42 +0100 | [diff] [blame] | 47 | preloader_console_init(); |
| 48 | |
Stefan Roese | d04fe8b | 2015-07-15 15:36:52 +0200 | [diff] [blame] | 49 | timer_init(); |
| 50 | |
Stefan Roese | e463bf3 | 2015-01-19 11:33:42 +0100 | [diff] [blame] | 51 | /* First init the serdes PHY's */ |
| 52 | serdes_phy_config(); |
| 53 | |
| 54 | /* Setup DDR */ |
| 55 | ddr3_init(); |
| 56 | |
| 57 | board_init_r(NULL, 0); |
| 58 | } |