Heiko Schocher | dd68a1d | 2013-08-05 16:00:38 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. |
| 3 | * Based on: |
| 4 | * U-Boot:include/configs/da850evm.h |
| 5 | * |
| 6 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ |
| 7 | * |
| 8 | * Based on davinci_dvevm.h. Original Copyrights follow: |
| 9 | * |
| 10 | * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
| 11 | * |
| 12 | * SPDX-License-Identifier: GPL-2.0+ |
| 13 | */ |
| 14 | |
| 15 | #ifndef __CONFIG_H |
| 16 | #define __CONFIG_H |
| 17 | |
| 18 | /* |
| 19 | * Board |
| 20 | */ |
| 21 | #define CONFIG_DRIVER_TI_EMAC |
| 22 | #define CONFIG_BARIX_IPAM390 |
| 23 | |
| 24 | /* |
| 25 | * SoC Configuration |
| 26 | */ |
| 27 | #define CONFIG_MACH_DAVINCI_DA850_EVM |
Heiko Schocher | dd68a1d | 2013-08-05 16:00:38 +0200 | [diff] [blame] | 28 | #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ |
| 29 | #define CONFIG_SOC_DA850 /* TI DA850 SoC */ |
| 30 | #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH |
| 31 | #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) |
| 32 | #define CONFIG_SYS_OSCIN_FREQ 24000000 |
| 33 | #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE |
| 34 | #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) |
Heiko Schocher | dd68a1d | 2013-08-05 16:00:38 +0200 | [diff] [blame] | 35 | #define CONFIG_SYS_TEXT_BASE 0xc1080000 |
| 36 | |
| 37 | /* |
| 38 | * Memory Info |
| 39 | */ |
| 40 | #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ |
| 41 | #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ |
| 42 | #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ |
| 43 | #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ |
| 44 | |
| 45 | /* memtest start addr */ |
| 46 | #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) |
| 47 | |
| 48 | /* memtest will be run on 16MB */ |
| 49 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 16 * 1024 * 1024) |
| 50 | |
| 51 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
| 52 | |
| 53 | #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ |
| 54 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ |
| 55 | DAVINCI_SYSCFG_SUSPSRC_UART2 | \ |
| 56 | DAVINCI_SYSCFG_SUSPSRC_UART0 | \ |
| 57 | DAVINCI_SYSCFG_SUSPSRC_EMAC) |
| 58 | |
| 59 | /* |
| 60 | * PLL configuration |
| 61 | */ |
| 62 | #define CONFIG_SYS_DV_CLKMODE 0 |
| 63 | #define CONFIG_SYS_DA850_PLL0_POSTDIV 1 |
| 64 | #define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 |
| 65 | #define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 |
| 66 | #define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 |
| 67 | #define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 |
| 68 | #define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 |
| 69 | #define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 |
| 70 | #define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 |
| 71 | |
| 72 | #define CONFIG_SYS_DA850_PLL1_POSTDIV 1 |
| 73 | #define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 |
| 74 | #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 |
| 75 | #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002 |
| 76 | |
| 77 | #define CONFIG_SYS_DA850_PLL0_PLLM 24 |
| 78 | #define CONFIG_SYS_DA850_PLL1_PLLM 24 |
| 79 | |
| 80 | /* |
| 81 | * DDR2 memory configuration |
| 82 | */ |
| 83 | #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ |
| 84 | DV_DDR_PHY_EXT_STRBEN | \ |
| 85 | (0x2 << DV_DDR_PHY_RD_LATENCY_SHIFT)) |
| 86 | #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000498 |
| 87 | |
| 88 | #define CONFIG_SYS_DA850_DDR2_SDBCR2 0x00000004 |
| 89 | #define CONFIG_SYS_DA850_DDR2_PBBPR 0x00000020 |
| 90 | |
Heiko Schocher | dd68a1d | 2013-08-05 16:00:38 +0200 | [diff] [blame] | 91 | #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ |
| 92 | (13 << DV_DDR_SDTMR1_RFC_SHIFT) | \ |
| 93 | (2 << DV_DDR_SDTMR1_RP_SHIFT) | \ |
| 94 | (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \ |
| 95 | (2 << DV_DDR_SDTMR1_WR_SHIFT) | \ |
| 96 | (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ |
| 97 | (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ |
| 98 | (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ |
| 99 | (1 << DV_DDR_SDTMR1_WTR_SHIFT)) |
| 100 | |
| 101 | #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ |
| 102 | (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ |
| 103 | (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ |
| 104 | (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ |
| 105 | (14 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ |
| 106 | (0xc7 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ |
| 107 | (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \ |
| 108 | (2 << DV_DDR_SDTMR2_CKE_SHIFT)) |
| 109 | |
| 110 | #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ |
| 111 | (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ |
| 112 | (1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) | \ |
| 113 | (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ |
| 114 | (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ |
| 115 | (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ |
| 116 | (2 << DV_DDR_SDCR_CL_SHIFT) | \ |
| 117 | (3 << DV_DDR_SDCR_IBANK_SHIFT) | \ |
| 118 | (2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) |
| 119 | |
Heiko Schocher | 203f391 | 2013-09-06 05:21:24 +0200 | [diff] [blame] | 120 | #define CONFIG_SYS_DA850_CS3CFG (DAVINCI_ABCR_WSETUP(1) | \ |
Heiko Schocher | dd68a1d | 2013-08-05 16:00:38 +0200 | [diff] [blame] | 121 | DAVINCI_ABCR_WSTROBE(2) | \ |
Heiko Schocher | 203f391 | 2013-09-06 05:21:24 +0200 | [diff] [blame] | 122 | DAVINCI_ABCR_WHOLD(0) | \ |
Heiko Schocher | dd68a1d | 2013-08-05 16:00:38 +0200 | [diff] [blame] | 123 | DAVINCI_ABCR_RSETUP(1) | \ |
Heiko Schocher | 203f391 | 2013-09-06 05:21:24 +0200 | [diff] [blame] | 124 | DAVINCI_ABCR_RSTROBE(2) | \ |
| 125 | DAVINCI_ABCR_RHOLD(1) | \ |
| 126 | DAVINCI_ABCR_TA(0) | \ |
Heiko Schocher | dd68a1d | 2013-08-05 16:00:38 +0200 | [diff] [blame] | 127 | DAVINCI_ABCR_ASIZE_8BIT) |
| 128 | |
Heiko Schocher | dd68a1d | 2013-08-05 16:00:38 +0200 | [diff] [blame] | 129 | /* |
| 130 | * Serial Driver info |
| 131 | */ |
Heiko Schocher | dd68a1d | 2013-08-05 16:00:38 +0200 | [diff] [blame] | 132 | #define CONFIG_SYS_NS16550_SERIAL |
| 133 | #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ |
| 134 | #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */ |
| 135 | #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) |
| 136 | #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ |
Heiko Schocher | dd68a1d | 2013-08-05 16:00:38 +0200 | [diff] [blame] | 137 | |
| 138 | /* |
| 139 | * Flash & Environment |
| 140 | */ |
| 141 | #define CONFIG_NAND_DAVINCI |
Heiko Schocher | dd68a1d | 2013-08-05 16:00:38 +0200 | [diff] [blame] | 142 | #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ |
| 143 | #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ |
| 144 | #define CONFIG_ENV_SIZE (128 << 10) |
| 145 | #define CONFIG_SYS_NAND_USE_FLASH_BBT |
| 146 | #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST |
| 147 | #define CONFIG_SYS_NAND_PAGE_2K |
| 148 | #define CONFIG_SYS_NAND_CS 3 |
| 149 | #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE |
| 150 | #define CONFIG_SYS_NAND_MASK_CLE 0x10 |
| 151 | #define CONFIG_SYS_NAND_MASK_ALE 0x8 |
| 152 | #undef CONFIG_SYS_NAND_HW_ECC |
| 153 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ |
| 154 | #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST |
Heiko Schocher | 203f391 | 2013-09-06 05:21:24 +0200 | [diff] [blame] | 155 | #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC |
Heiko Schocher | dd68a1d | 2013-08-05 16:00:38 +0200 | [diff] [blame] | 156 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE |
| 157 | #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) |
| 158 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) |
| 159 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 |
| 160 | #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x120000 |
| 161 | #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 |
| 162 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST |
| 163 | #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ |
| 164 | CONFIG_SYS_NAND_U_BOOT_SIZE - \ |
| 165 | CONFIG_SYS_MALLOC_LEN - \ |
| 166 | GENERATED_GBL_DATA_SIZE) |
| 167 | #define CONFIG_SYS_NAND_ECCPOS { \ |
Heiko Schocher | 203f391 | 2013-09-06 05:21:24 +0200 | [diff] [blame] | 168 | 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ |
| 169 | 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ |
| 170 | 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ |
| 171 | 54, 55, 56, 57, 58, 59, 60, 61, 62, 63} |
Heiko Schocher | dd68a1d | 2013-08-05 16:00:38 +0200 | [diff] [blame] | 172 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 |
| 173 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 |
| 174 | #define CONFIG_SYS_NAND_ECCSIZE 512 |
| 175 | #define CONFIG_SYS_NAND_ECCBYTES 10 |
| 176 | #define CONFIG_SYS_NAND_OOBSIZE 64 |
Heiko Schocher | dd68a1d | 2013-08-05 16:00:38 +0200 | [diff] [blame] | 177 | #define CONFIG_SPL_NAND_BASE |
| 178 | #define CONFIG_SPL_NAND_DRIVERS |
| 179 | #define CONFIG_SPL_NAND_ECC |
| 180 | #define CONFIG_SPL_NAND_SIMPLE |
| 181 | #define CONFIG_SPL_NAND_LOAD |
| 182 | |
| 183 | /* |
| 184 | * Network & Ethernet Configuration |
| 185 | */ |
| 186 | #ifdef CONFIG_DRIVER_TI_EMAC |
| 187 | #define CONFIG_DRIVER_TI_EMAC_USE_RMII |
| 188 | #define CONFIG_BOOTP_DEFAULT |
| 189 | #define CONFIG_BOOTP_DNS |
| 190 | #define CONFIG_BOOTP_DNS2 |
| 191 | #define CONFIG_BOOTP_SEND_HOSTNAME |
| 192 | #define CONFIG_NET_RETRY_COUNT 10 |
| 193 | #endif |
| 194 | |
| 195 | /* |
| 196 | * U-Boot general configuration |
| 197 | */ |
| 198 | #define CONFIG_MISC_INIT_R |
Heiko Schocher | dd68a1d | 2013-08-05 16:00:38 +0200 | [diff] [blame] | 199 | #define CONFIG_BOOTFILE "uImage" /* Boot file name */ |
Heiko Schocher | dd68a1d | 2013-08-05 16:00:38 +0200 | [diff] [blame] | 200 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 201 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
| 202 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 203 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ |
| 204 | #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) |
Heiko Schocher | dd68a1d | 2013-08-05 16:00:38 +0200 | [diff] [blame] | 205 | #define CONFIG_AUTO_COMPLETE |
Heiko Schocher | dd68a1d | 2013-08-05 16:00:38 +0200 | [diff] [blame] | 206 | #define CONFIG_CMDLINE_EDITING |
| 207 | #define CONFIG_SYS_LONGHELP |
| 208 | #define CONFIG_CRC32_VERIFY |
| 209 | #define CONFIG_MX_CYCLIC |
| 210 | |
| 211 | /* |
| 212 | * Linux Information |
| 213 | */ |
| 214 | #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) |
| 215 | #define CONFIG_HWCONFIG /* enable hwconfig */ |
| 216 | #define CONFIG_CMDLINE_TAG |
| 217 | #define CONFIG_REVISION_TAG |
| 218 | #define CONFIG_SETUP_MEMORY_TAGS |
Heiko Schocher | dd68a1d | 2013-08-05 16:00:38 +0200 | [diff] [blame] | 219 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Heiko Schocher | 203f391 | 2013-09-06 05:21:24 +0200 | [diff] [blame] | 220 | "defbootargs=setenv bootargs mem=128M console=ttyS0,115200n8 " \ |
| 221 | "root=/dev/mtdblock5 rw noinitrd " \ |
| 222 | "rootfstype=jffs2 noinitrd\0" \ |
Heiko Schocher | dd68a1d | 2013-08-05 16:00:38 +0200 | [diff] [blame] | 223 | "hwconfig=dsp:wake=yes\0" \ |
Heiko Schocher | 203f391 | 2013-09-06 05:21:24 +0200 | [diff] [blame] | 224 | "bootcmd=nboot kernel;run defbootargs addmtd;bootm 0xc0700000\0" \ |
| 225 | "bootfile=uImage\0" \ |
Heiko Schocher | dd68a1d | 2013-08-05 16:00:38 +0200 | [diff] [blame] | 226 | "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ |
Heiko Schocher | 203f391 | 2013-09-06 05:21:24 +0200 | [diff] [blame] | 227 | "mtddevname=uboot-env\0" \ |
| 228 | "mtddevnum=0\0" \ |
Heiko Schocher | dd68a1d | 2013-08-05 16:00:38 +0200 | [diff] [blame] | 229 | "mtdids=" MTDIDS_DEFAULT "\0" \ |
| 230 | "mtdparts=" MTDPARTS_DEFAULT "\0" \ |
Heiko Schocher | 203f391 | 2013-09-06 05:21:24 +0200 | [diff] [blame] | 231 | "u-boot=/tftpboot/ipam390/u-boot.ais\0" \ |
| 232 | "upd_uboot=tftp c0000000 ${u-boot};nand erase.part u-boot;" \ |
| 233 | "nand write c0000000 20000 ${filesize}\0" \ |
Heiko Schocher | dd68a1d | 2013-08-05 16:00:38 +0200 | [diff] [blame] | 234 | "setbootparms=nand read c0100000 200000 400000;" \ |
Heiko Schocher | 203f391 | 2013-09-06 05:21:24 +0200 | [diff] [blame] | 235 | "run defbootargs addmtd;" \ |
Heiko Schocher | dd68a1d | 2013-08-05 16:00:38 +0200 | [diff] [blame] | 236 | "spl export atags c0100000;" \ |
| 237 | "nand erase.part bootparms;" \ |
| 238 | "nand write c0000100 180000 20000\0" \ |
| 239 | "\0" |
| 240 | |
| 241 | /* |
| 242 | * U-Boot commands |
| 243 | */ |
Heiko Schocher | dd68a1d | 2013-08-05 16:00:38 +0200 | [diff] [blame] | 244 | #define CONFIG_CMD_ENV |
Heiko Schocher | dd68a1d | 2013-08-05 16:00:38 +0200 | [diff] [blame] | 245 | #define CONFIG_CMD_SAVES |
Heiko Schocher | dd68a1d | 2013-08-05 16:00:38 +0200 | [diff] [blame] | 246 | |
| 247 | #ifdef CONFIG_CMD_BDI |
| 248 | #define CONFIG_CLOCKS |
| 249 | #endif |
| 250 | |
| 251 | #ifndef CONFIG_DRIVER_TI_EMAC |
Heiko Schocher | dd68a1d | 2013-08-05 16:00:38 +0200 | [diff] [blame] | 252 | #endif |
| 253 | |
| 254 | #define CONFIG_CMD_NAND |
| 255 | #define CONFIG_CMD_NAND_TRIMFFS |
| 256 | |
| 257 | #define CONFIG_CMD_MTDPARTS |
| 258 | #define CONFIG_MTD_DEVICE |
| 259 | #define CONFIG_MTD_PARTITIONS |
| 260 | #define CONFIG_LZO |
| 261 | #define CONFIG_RBTREE |
Heiko Schocher | dd68a1d | 2013-08-05 16:00:38 +0200 | [diff] [blame] | 262 | #define CONFIG_CMD_UBIFS |
| 263 | |
| 264 | #define MTDIDS_NAME_STR "davinci_nand.0" |
| 265 | #define MTDIDS_DEFAULT "nand0=" MTDIDS_NAME_STR |
| 266 | #define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \ |
| 267 | "128k(u-boot-env)," \ |
| 268 | "1408k(u-boot)," \ |
| 269 | "128k(bootparms)," \ |
| 270 | "384k(factory-info)," \ |
| 271 | "4M(kernel)," \ |
| 272 | "-(rootfs)" |
| 273 | |
| 274 | /* defines for SPL */ |
Heiko Schocher | dd68a1d | 2013-08-05 16:00:38 +0200 | [diff] [blame] | 275 | #define CONFIG_SPL_FRAMEWORK |
| 276 | #define CONFIG_SPL_BOARD_INIT |
| 277 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ |
| 278 | CONFIG_SYS_MALLOC_LEN) |
| 279 | #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN |
Heiko Schocher | dd68a1d | 2013-08-05 16:00:38 +0200 | [diff] [blame] | 280 | #define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-ipam390.lds" |
| 281 | #define CONFIG_SPL_STACK 0x8001ff00 |
| 282 | #define CONFIG_SPL_TEXT_BASE 0x80000000 |
| 283 | #define CONFIG_SPL_MAX_SIZE 0x20000 |
| 284 | #define CONFIG_SPL_MAX_FOOTPRINT 32768 |
| 285 | |
| 286 | /* additions for new relocation code, must added to all boards */ |
| 287 | #define CONFIG_SYS_SDRAM_BASE 0xc0000000 |
| 288 | |
| 289 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ |
| 290 | GENERATED_GBL_DATA_SIZE) |
| 291 | |
| 292 | /* add FALCON boot mode */ |
| 293 | #define CONFIG_CMD_SPL |
Heiko Schocher | dd68a1d | 2013-08-05 16:00:38 +0200 | [diff] [blame] | 294 | #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 |
| 295 | #define CONFIG_SYS_SPL_ARGS_ADDR LINUX_BOOT_PARAM_ADDR |
| 296 | #define CONFIG_CMD_SPL_NAND_OFS 0x00180000 |
| 297 | #define CONFIG_CMD_SPL_WRITE_SIZE 0x400 |
| 298 | |
| 299 | /* GPIO support */ |
Heiko Schocher | dd68a1d | 2013-08-05 16:00:38 +0200 | [diff] [blame] | 300 | #define CONFIG_DA8XX_GPIO |
| 301 | #define CONFIG_IPAM390_GPIO_BOOTMODE ((16 * 7) + 14) |
| 302 | |
| 303 | #define CONFIG_SHOW_BOOT_PROGRESS |
| 304 | #define CONFIG_IPAM390_GPIO_LED_RED ((16 * 7) + 11) |
| 305 | #define CONFIG_IPAM390_GPIO_LED_GREEN ((16 * 7) + 12) |
| 306 | |
| 307 | #endif /* __CONFIG_H */ |