Jagan Teki | 72e5750 | 2016-12-13 17:56:52 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2016 Amarula Solutions B.V. |
| 3 | * Copyright (C) 2016 Engicam S.r.l. |
| 4 | * Author: Jagan Teki <jagan@amarulasolutions.com> |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 7 | */ |
| 8 | |
| 9 | #include <common.h> |
Jagan Teki | 54cc63f | 2017-05-07 02:43:03 +0530 | [diff] [blame] | 10 | #include <mmc.h> |
Jagan Teki | 72e5750 | 2016-12-13 17:56:52 +0100 | [diff] [blame] | 11 | |
| 12 | #include <asm/io.h> |
| 13 | #include <asm/gpio.h> |
| 14 | #include <linux/sizes.h> |
| 15 | |
| 16 | #include <asm/arch/clock.h> |
Jagan Teki | 55c495c | 2016-12-13 17:56:55 +0100 | [diff] [blame] | 17 | #include <asm/arch/crm_regs.h> |
Jagan Teki | 72e5750 | 2016-12-13 17:56:52 +0100 | [diff] [blame] | 18 | #include <asm/arch/iomux.h> |
| 19 | #include <asm/arch/mx6-pins.h> |
| 20 | #include <asm/arch/sys_proto.h> |
| 21 | #include <asm/imx-common/iomux-v3.h> |
| 22 | |
| 23 | DECLARE_GLOBAL_DATA_PTR; |
| 24 | |
| 25 | #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| 26 | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ |
| 27 | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| 28 | |
| 29 | static iomux_v3_cfg_t const uart1_pads[] = { |
| 30 | MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 31 | MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 32 | }; |
| 33 | |
| 34 | int board_early_init_f(void) |
| 35 | { |
| 36 | imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); |
| 37 | |
| 38 | return 0; |
| 39 | } |
| 40 | |
Jagan Teki | 55c495c | 2016-12-13 17:56:55 +0100 | [diff] [blame] | 41 | #ifdef CONFIG_NAND_MXS |
| 42 | |
| 43 | #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) |
| 44 | #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ |
| 45 | PAD_CTL_SRE_FAST) |
| 46 | #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) |
| 47 | |
| 48 | static iomux_v3_cfg_t const nand_pads[] = { |
| 49 | MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| 50 | MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| 51 | MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| 52 | MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| 53 | MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| 54 | MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| 55 | MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| 56 | MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| 57 | MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| 58 | MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| 59 | MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| 60 | MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| 61 | MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| 62 | MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| 63 | MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| 64 | }; |
| 65 | |
| 66 | static void setup_gpmi_nand(void) |
| 67 | { |
| 68 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| 69 | |
| 70 | /* config gpmi nand iomux */ |
| 71 | imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); |
| 72 | |
| 73 | clrbits_le32(&mxc_ccm->CCGR4, |
| 74 | MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | |
| 75 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | |
| 76 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | |
| 77 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | |
| 78 | MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); |
| 79 | |
| 80 | /* |
| 81 | * config gpmi and bch clock to 100 MHz |
| 82 | * bch/gpmi select PLL2 PFD2 400M |
| 83 | * 100M = 400M / 4 |
| 84 | */ |
| 85 | clrbits_le32(&mxc_ccm->cscmr1, |
| 86 | MXC_CCM_CSCMR1_BCH_CLK_SEL | |
| 87 | MXC_CCM_CSCMR1_GPMI_CLK_SEL); |
| 88 | clrsetbits_le32(&mxc_ccm->cscdr1, |
| 89 | MXC_CCM_CSCDR1_BCH_PODF_MASK | |
| 90 | MXC_CCM_CSCDR1_GPMI_PODF_MASK, |
| 91 | (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | |
| 92 | (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)); |
| 93 | |
| 94 | /* enable gpmi and bch clock gating */ |
| 95 | setbits_le32(&mxc_ccm->CCGR4, |
| 96 | MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | |
| 97 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | |
| 98 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | |
| 99 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | |
| 100 | MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); |
| 101 | |
| 102 | /* enable apbh clock gating */ |
| 103 | setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); |
| 104 | } |
| 105 | #endif /* CONFIG_NAND_MXS */ |
| 106 | |
Jagan Teki | 54cc63f | 2017-05-07 02:43:03 +0530 | [diff] [blame] | 107 | #ifdef CONFIG_ENV_IS_IN_MMC |
| 108 | static void mmc_late_init(void) |
| 109 | { |
| 110 | char cmd[32]; |
| 111 | char mmcblk[32]; |
| 112 | u32 dev_no = mmc_get_env_dev(); |
| 113 | |
| 114 | setenv_ulong("mmcdev", dev_no); |
| 115 | |
| 116 | /* Set mmcblk env */ |
| 117 | sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no); |
| 118 | setenv("mmcroot", mmcblk); |
| 119 | |
| 120 | sprintf(cmd, "mmc dev %d", dev_no); |
| 121 | run_command(cmd, 0); |
| 122 | } |
| 123 | #endif |
| 124 | |
Jagan Teki | 3061eb3 | 2017-05-07 02:43:02 +0530 | [diff] [blame] | 125 | int board_late_init(void) |
| 126 | { |
| 127 | switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >> |
| 128 | IMX6_BMODE_SHIFT) { |
| 129 | case IMX6_BMODE_SD: |
| 130 | case IMX6_BMODE_ESD: |
Jagan Teki | 54cc63f | 2017-05-07 02:43:03 +0530 | [diff] [blame] | 131 | #ifdef CONFIG_ENV_IS_IN_MMC |
| 132 | mmc_late_init(); |
| 133 | #endif |
Jagan Teki | 3061eb3 | 2017-05-07 02:43:02 +0530 | [diff] [blame] | 134 | setenv("modeboot", "mmcboot"); |
| 135 | break; |
| 136 | case IMX6_BMODE_NAND: |
| 137 | setenv("modeboot", "nandboot"); |
| 138 | break; |
| 139 | default: |
| 140 | setenv("modeboot", ""); |
| 141 | break; |
| 142 | } |
| 143 | |
Jagan Teki | 38b08b4 | 2017-05-07 02:43:04 +0530 | [diff] [blame] | 144 | if (is_mx6ul()) |
| 145 | setenv("fdt_file", "imx6ul-geam-kit.dtb"); |
| 146 | |
Jagan Teki | 3061eb3 | 2017-05-07 02:43:02 +0530 | [diff] [blame] | 147 | return 0; |
| 148 | } |
| 149 | |
Jagan Teki | 72e5750 | 2016-12-13 17:56:52 +0100 | [diff] [blame] | 150 | int board_init(void) |
| 151 | { |
| 152 | /* Address of boot parameters */ |
| 153 | gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
| 154 | |
Jagan Teki | 55c495c | 2016-12-13 17:56:55 +0100 | [diff] [blame] | 155 | #ifdef CONFIG_NAND_MXS |
| 156 | setup_gpmi_nand(); |
| 157 | #endif |
| 158 | |
Jagan Teki | 72e5750 | 2016-12-13 17:56:52 +0100 | [diff] [blame] | 159 | return 0; |
| 160 | } |
| 161 | |
| 162 | int dram_init(void) |
| 163 | { |
| 164 | gd->ram_size = imx_ddr_size(); |
| 165 | |
| 166 | return 0; |
| 167 | } |
| 168 | |
| 169 | #ifdef CONFIG_SPL_BUILD |
| 170 | #include <libfdt.h> |
| 171 | #include <spl.h> |
| 172 | |
| 173 | #include <asm/arch/crm_regs.h> |
| 174 | #include <asm/arch/mx6-ddr.h> |
| 175 | |
| 176 | /* MMC board initialization is needed till adding DM support in SPL */ |
| 177 | #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC) |
| 178 | #include <mmc.h> |
| 179 | #include <fsl_esdhc.h> |
| 180 | |
| 181 | #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| 182 | PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ |
| 183 | PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| 184 | |
| 185 | static iomux_v3_cfg_t const usdhc1_pads[] = { |
| 186 | MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 187 | MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 188 | MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 189 | MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 190 | MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 191 | MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 192 | |
| 193 | /* VSELECT */ |
| 194 | MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 195 | /* CD */ |
| 196 | MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 197 | /* RST_B */ |
| 198 | MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 199 | }; |
| 200 | |
| 201 | #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1) |
| 202 | |
| 203 | struct fsl_esdhc_cfg usdhc_cfg[1] = { |
| 204 | {USDHC1_BASE_ADDR, 0, 4}, |
| 205 | }; |
| 206 | |
| 207 | int board_mmc_getcd(struct mmc *mmc) |
| 208 | { |
| 209 | struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
| 210 | int ret = 0; |
| 211 | |
| 212 | switch (cfg->esdhc_base) { |
| 213 | case USDHC1_BASE_ADDR: |
| 214 | ret = !gpio_get_value(USDHC1_CD_GPIO); |
| 215 | break; |
| 216 | } |
| 217 | |
| 218 | return ret; |
| 219 | } |
| 220 | |
| 221 | int board_mmc_init(bd_t *bis) |
| 222 | { |
| 223 | int i, ret; |
| 224 | |
| 225 | /* |
| 226 | * According to the board_mmc_init() the following map is done: |
| 227 | * (U-boot device node) (Physical Port) |
| 228 | * mmc0 USDHC1 |
| 229 | */ |
| 230 | for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { |
| 231 | switch (i) { |
| 232 | case 0: |
| 233 | imx_iomux_v3_setup_multiple_pads( |
| 234 | usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); |
| 235 | gpio_direction_input(USDHC1_CD_GPIO); |
| 236 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); |
| 237 | break; |
| 238 | default: |
| 239 | printf("Warning - USDHC%d controller not supporting\n", |
| 240 | i + 1); |
| 241 | return 0; |
| 242 | } |
| 243 | |
| 244 | ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); |
| 245 | if (ret) { |
| 246 | printf("Warning: failed to initialize mmc dev %d\n", i); |
| 247 | return ret; |
| 248 | } |
| 249 | } |
| 250 | |
| 251 | return 0; |
| 252 | } |
| 253 | #endif /* CONFIG_FSL_ESDHC */ |
| 254 | |
| 255 | static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { |
| 256 | .grp_addds = 0x00000030, |
| 257 | .grp_ddrmode_ctl = 0x00020000, |
| 258 | .grp_b0ds = 0x00000030, |
| 259 | .grp_ctlds = 0x00000030, |
| 260 | .grp_b1ds = 0x00000030, |
| 261 | .grp_ddrpke = 0x00000000, |
| 262 | .grp_ddrmode = 0x00020000, |
| 263 | .grp_ddr_type = 0x000c0000, |
| 264 | }; |
| 265 | |
| 266 | static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { |
| 267 | .dram_dqm0 = 0x00000030, |
| 268 | .dram_dqm1 = 0x00000030, |
| 269 | .dram_ras = 0x00000030, |
| 270 | .dram_cas = 0x00000030, |
| 271 | .dram_odt0 = 0x00000030, |
| 272 | .dram_odt1 = 0x00000030, |
| 273 | .dram_sdba2 = 0x00000000, |
| 274 | .dram_sdclk_0 = 0x00000008, |
| 275 | .dram_sdqs0 = 0x00000038, |
| 276 | .dram_sdqs1 = 0x00000030, |
| 277 | .dram_reset = 0x00000030, |
| 278 | }; |
| 279 | |
| 280 | static struct mx6_mmdc_calibration mx6_mmcd_calib = { |
| 281 | .p0_mpwldectrl0 = 0x00070007, |
| 282 | .p0_mpdgctrl0 = 0x41490145, |
| 283 | .p0_mprddlctl = 0x40404546, |
| 284 | .p0_mpwrdlctl = 0x4040524D, |
| 285 | }; |
| 286 | |
| 287 | struct mx6_ddr_sysinfo ddr_sysinfo = { |
| 288 | .dsize = 0, |
| 289 | .cs_density = 20, |
| 290 | .ncs = 1, |
| 291 | .cs1_mirror = 0, |
| 292 | .rtt_wr = 2, |
| 293 | .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ |
| 294 | .walat = 1, /* Write additional latency */ |
| 295 | .ralat = 5, /* Read additional latency */ |
| 296 | .mif3_mode = 3, /* Command prediction working mode */ |
| 297 | .bi_on = 1, /* Bank interleaving enabled */ |
| 298 | .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ |
| 299 | .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ |
| 300 | .ddr_type = DDR_TYPE_DDR3, |
| 301 | }; |
| 302 | |
| 303 | static struct mx6_ddr3_cfg mem_ddr = { |
| 304 | .mem_speed = 800, |
| 305 | .density = 4, |
| 306 | .width = 16, |
| 307 | .banks = 8, |
| 308 | .rowaddr = 13, |
| 309 | .coladdr = 10, |
| 310 | .pagesz = 2, |
| 311 | .trcd = 1375, |
| 312 | .trcmin = 4875, |
| 313 | .trasmin = 3500, |
| 314 | }; |
| 315 | |
| 316 | static void ccgr_init(void) |
| 317 | { |
| 318 | struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| 319 | |
| 320 | writel(0xFFFFFFFF, &ccm->CCGR0); |
| 321 | writel(0xFFFFFFFF, &ccm->CCGR1); |
| 322 | writel(0xFFFFFFFF, &ccm->CCGR2); |
| 323 | writel(0xFFFFFFFF, &ccm->CCGR3); |
| 324 | writel(0xFFFFFFFF, &ccm->CCGR4); |
| 325 | writel(0xFFFFFFFF, &ccm->CCGR5); |
| 326 | writel(0xFFFFFFFF, &ccm->CCGR6); |
| 327 | writel(0xFFFFFFFF, &ccm->CCGR7); |
| 328 | } |
| 329 | |
| 330 | static void spl_dram_init(void) |
| 331 | { |
| 332 | mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); |
| 333 | mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); |
| 334 | } |
| 335 | |
| 336 | void board_init_f(ulong dummy) |
| 337 | { |
| 338 | /* setup AIPS and disable watchdog */ |
| 339 | arch_cpu_init(); |
| 340 | |
| 341 | ccgr_init(); |
| 342 | |
| 343 | /* iomux and setup of i2c */ |
| 344 | board_early_init_f(); |
| 345 | |
| 346 | /* setup GP timer */ |
| 347 | timer_init(); |
| 348 | |
| 349 | /* UART clocks enabled and gd valid - init serial console */ |
| 350 | preloader_console_init(); |
| 351 | |
| 352 | /* DDR initialization */ |
| 353 | spl_dram_init(); |
| 354 | |
| 355 | /* Clear the BSS. */ |
| 356 | memset(__bss_start, 0, __bss_end - __bss_start); |
| 357 | |
| 358 | /* load/boot image from boot device */ |
| 359 | board_init_r(NULL, 0); |
| 360 | } |
| 361 | #endif /* CONFIG_SPL_BUILD */ |