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Wolfgang Denk52744b42013-07-28 22:12:45 +02001/*
Wolfgang Denk815c9672013-09-17 11:24:06 +02002 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
Wolfgang Denk52744b42013-07-28 22:12:45 +02003 */
wdenk37bd3212002-11-03 11:21:28 +00004/*-----------------------------------------------------------------------------
5 * Function: ext_bus_cntlr_init
6 * Description: Initializes the External Bus Controller for the external
7 * peripherals. IMPORTANT: For pass1 this code must run from
8 * cache since you can not reliably change a peripheral banks
9 * timing register (pbxap) while running code from that bank.
10 * For ex., since we are running from ROM on bank 0, we can NOT
11 * execute the code that modifies bank 0 timings from ROM, so
12 * we run it from cache.
13 * Bank 0 - Flash or Multi Purpose Socket
14 * Bank 1 - Multi Purpose Socket or Flash (set in C-Code)
15 * Bank 2 - UART 1 (set in C-Code)
16 * Bank 3 - UART 2 (set in C-Code)
17 * Bank 4 - not used
18 * Bank 5 - not used
19 * Bank 6 - not used
20 * Bank 7 - PLD Register
21 *-----------------------------------------------------------------------------*/
wdenk37bd3212002-11-03 11:21:28 +000022#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
23
24#include <configs/MIP405.h>
25#include <ppc_asm.tmpl>
26#include <ppc_defs.h>
27
28#include <asm/cache.h>
29#include <asm/mmu.h>
Stefan Roese8cb251a2010-09-12 06:21:37 +020030#include <asm/ppc4xx.h>
wdenk37bd3212002-11-03 11:21:28 +000031#include "mip405.h"
32
33
wdenke39c2842003-06-04 15:05:30 +000034 .globl ext_bus_cntlr_init
wdenk37bd3212002-11-03 11:21:28 +000035ext_bus_cntlr_init:
wdenke39c2842003-06-04 15:05:30 +000036 mflr r4 /* save link register */
Stefan Roese918010a2009-09-09 16:25:29 +020037 mfdcr r3,CPC0_PSR /* get strapping reg */
wdenke39c2842003-06-04 15:05:30 +000038 andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */
39 bnelr /* jump back if PCI boot */
40
wdenk37bd3212002-11-03 11:21:28 +000041 bl ..getAddr
42..getAddr:
43 mflr r3 /* get address of ..getAddr */
44 mtlr r4 /* restore link register */
45 addi r4,0,14 /* set ctr to 14; used to prefetch */
46 mtctr r4 /* 14 cache lines to fit this function */
wdenk57b2d802003-06-27 21:31:46 +000047 /* in cache (gives us 8x14=112 instrctns) */
wdenk37bd3212002-11-03 11:21:28 +000048..ebcloop:
49 icbt r0,r3 /* prefetch cache line for addr in r3 */
50 addi r3,r3,32 /* move to next cache line */
51 bdnz ..ebcloop /* continue for 14 cache lines */
52
53 /*-------------------------------------------------------------------
54 * Delay to ensure all accesses to ROM are complete before changing
55 * bank 0 timings.
56 *------------------------------------------------------------------- */
57 addis r3,0,0x0
58 ori r3,r3,0xA000
59 mtctr r3
60..spinlp:
61 bdnz ..spinlp /* spin loop */
62
63 /*-----------------------------------------------------------------------
64 * decide boot up mode
65 *----------------------------------------------------------------------- */
Stefan Roese918010a2009-09-09 16:25:29 +020066 addi r4,0,PB0CR
67 mtdcr EBC0_CFGADDR,r4
68 mfdcr r4,EBC0_CFGDATA
wdenk37bd3212002-11-03 11:21:28 +000069
70 andi. r0, r4, 0x2000 /* mask out irrelevant bits */
wdenk2c9b05d2003-09-10 22:30:53 +000071 beq 0f /* jump if 8 bit bus width */
wdenk37bd3212002-11-03 11:21:28 +000072
wdenk2c9b05d2003-09-10 22:30:53 +000073 /* setup 16 bit things
wdenk37bd3212002-11-03 11:21:28 +000074 *-----------------------------------------------------------------------
75 * Memory Bank 0 (16 Bit Flash) initialization
76 *---------------------------------------------------------------------- */
77
Stefan Roese918010a2009-09-09 16:25:29 +020078 addi r4,0,PB1AP
79 mtdcr EBC0_CFGADDR,r4
wdenk37bd3212002-11-03 11:21:28 +000080 addis r4,0,(FLASH_AP_B)@h
81 ori r4,r4,(FLASH_AP_B)@l
Stefan Roese918010a2009-09-09 16:25:29 +020082 mtdcr EBC0_CFGDATA,r4
wdenk37bd3212002-11-03 11:21:28 +000083
Stefan Roese918010a2009-09-09 16:25:29 +020084 addi r4,0,PB0CR
85 mtdcr EBC0_CFGADDR,r4
wdenk37bd3212002-11-03 11:21:28 +000086 /* BS=0x010(4MB),BU=0x3(R/W), */
wdenk37bd3212002-11-03 11:21:28 +000087 addis r4,0,(FLASH_CR_B)@h
88 ori r4,r4,(FLASH_CR_B)@l
Stefan Roese918010a2009-09-09 16:25:29 +020089 mtdcr EBC0_CFGDATA,r4
wdenk37bd3212002-11-03 11:21:28 +000090 b 1f
91
920:
93
wdenk57b2d802003-06-27 21:31:46 +000094 /* 8Bit boot mode: */
wdenk37bd3212002-11-03 11:21:28 +000095 /*-----------------------------------------------------------------------
wdenk57b2d802003-06-27 21:31:46 +000096 * Memory Bank 0 Multi Purpose Socket initialization
97 *----------------------------------------------------------------------- */
wdenk37bd3212002-11-03 11:21:28 +000098 /* 0x7F8FFE80 slowest boot */
Stefan Roese918010a2009-09-09 16:25:29 +020099 addi r4,0,PB1AP
100 mtdcr EBC0_CFGADDR,r4
wdenk37bd3212002-11-03 11:21:28 +0000101 addis r4,0,(MPS_AP_B)@h
102 ori r4,r4,(MPS_AP_B)@l
Stefan Roese918010a2009-09-09 16:25:29 +0200103 mtdcr EBC0_CFGDATA,r4
wdenk37bd3212002-11-03 11:21:28 +0000104
Stefan Roese918010a2009-09-09 16:25:29 +0200105 addi r4,0,PB0CR
106 mtdcr EBC0_CFGADDR,r4
wdenk37bd3212002-11-03 11:21:28 +0000107 /* BS=0x010(4MB),BU=0x3(R/W), */
wdenk37bd3212002-11-03 11:21:28 +0000108 addis r4,0,(MPS_CR_B)@h
109 ori r4,r4,(MPS_CR_B)@l
110
Stefan Roese918010a2009-09-09 16:25:29 +0200111 mtdcr EBC0_CFGDATA,r4
wdenk37bd3212002-11-03 11:21:28 +0000112
113
1141:
115 /*-----------------------------------------------------------------------
116 * Memory Bank 2-3-4-5-6 (not used) initialization
117 *-----------------------------------------------------------------------*/
Stefan Roese918010a2009-09-09 16:25:29 +0200118 addi r4,0,PB1CR
119 mtdcr EBC0_CFGADDR,r4
wdenk37bd3212002-11-03 11:21:28 +0000120 addis r4,0,0x0000
121 ori r4,r4,0x0000
Stefan Roese918010a2009-09-09 16:25:29 +0200122 mtdcr EBC0_CFGDATA,r4
wdenk37bd3212002-11-03 11:21:28 +0000123
Stefan Roese918010a2009-09-09 16:25:29 +0200124 addi r4,0,PB2CR
125 mtdcr EBC0_CFGADDR,r4
wdenk37bd3212002-11-03 11:21:28 +0000126 addis r4,0,0x0000
127 ori r4,r4,0x0000
Stefan Roese918010a2009-09-09 16:25:29 +0200128 mtdcr EBC0_CFGDATA,r4
wdenk37bd3212002-11-03 11:21:28 +0000129
Stefan Roese918010a2009-09-09 16:25:29 +0200130 addi r4,0,PB3CR
131 mtdcr EBC0_CFGADDR,r4
wdenk37bd3212002-11-03 11:21:28 +0000132 addis r4,0,0x0000
133 ori r4,r4,0x0000
Stefan Roese918010a2009-09-09 16:25:29 +0200134 mtdcr EBC0_CFGDATA,r4
wdenk37bd3212002-11-03 11:21:28 +0000135
Stefan Roese918010a2009-09-09 16:25:29 +0200136 addi r4,0,PB4CR
137 mtdcr EBC0_CFGADDR,r4
wdenk37bd3212002-11-03 11:21:28 +0000138 addis r4,0,0x0000
139 ori r4,r4,0x0000
Stefan Roese918010a2009-09-09 16:25:29 +0200140 mtdcr EBC0_CFGDATA,r4
wdenk37bd3212002-11-03 11:21:28 +0000141
Stefan Roese918010a2009-09-09 16:25:29 +0200142 addi r4,0,PB5CR
143 mtdcr EBC0_CFGADDR,r4
wdenk37bd3212002-11-03 11:21:28 +0000144 addis r4,0,0x0000
145 ori r4,r4,0x0000
Stefan Roese918010a2009-09-09 16:25:29 +0200146 mtdcr EBC0_CFGDATA,r4
wdenk37bd3212002-11-03 11:21:28 +0000147
Stefan Roese918010a2009-09-09 16:25:29 +0200148 addi r4,0,PB6CR
149 mtdcr EBC0_CFGADDR,r4
wdenk37bd3212002-11-03 11:21:28 +0000150 addis r4,0,0x0000
151 ori r4,r4,0x0000
Stefan Roese918010a2009-09-09 16:25:29 +0200152 mtdcr EBC0_CFGDATA,r4
wdenk37bd3212002-11-03 11:21:28 +0000153
Stefan Roese918010a2009-09-09 16:25:29 +0200154 addi r4,0,PB7CR
155 mtdcr EBC0_CFGADDR,r4
wdenk37bd3212002-11-03 11:21:28 +0000156 addis r4,0,0x0000
157 ori r4,r4,0x0000
Stefan Roese918010a2009-09-09 16:25:29 +0200158 mtdcr EBC0_CFGDATA,r4
wdenk2c9b05d2003-09-10 22:30:53 +0000159 nop /* pass2 DCR errata #8 */
wdenk37bd3212002-11-03 11:21:28 +0000160 blr
161
wdenke39c2842003-06-04 15:05:30 +0000162#if defined(CONFIG_BOOT_PCI)
163 .section .bootpg,"ax"
164 .globl _start_pci
165/*******************************************
166 */
167
168_start_pci:
169 /* first handle errata #68 / PCI_18 */
170 iccci r0, r0 /* invalidate I-cache */
171 lis r31, 0
172 mticcr r31 /* ICCR = 0 (all uncachable) */
173 isync
174
175 mfccr0 r28 /* set CCR0[24] = 1 */
176 ori r28, r28, 0x0080
177 mtccr0 r28
178
179 /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */
180 lis r28, 0xEF40
181 addi r28, r28, 0x0004
182 stw r31, 0x0C(r28) /* clear PMM0PCIHA */
183 lis r29, 0xFFF8 /* open 512 kByte */
184 addi r29, r29, 0x0001/* and enable this region */
185 stwbrx r29, r0, r28 /* write PMM0MA */
186
187 lis r28, 0xEEC0 /* address of PCIC0_CFGADDR */
188 addi r29, r28, 4 /* add 4 to r29 -> PCIC0_CFGDATA */
189
190 lis r31, 0x8000 /* set en bit bus 0 */
191 ori r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */
192 stwbrx r31, r0, r28 /* write it */
193
194 lwbrx r31, r0, r29 /* load XBCS register */
195 oris r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */
196 stwbrx r31, r0, r29 /* write back XBCS register */
197
198 nop
199 nop
200 b _start /* normal start */
201#endif