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git01.mediatek.com / filogic / uboot / 0904eb26861fe601d1f9218cb85a2bd426c59157 / . / board / Marvell / include / core.h
blob: 3119d0a073e0087249107742b8f36d33027be5da [file] [log] [blame]
wdenk5da7f2f2004-01-03 00:43:19 +0000[diff] [blame]1/* Core.h - Basic core logic functions and definitions */
2
3/* Copyright Galileo Technology. */
4
5/*
6DESCRIPTION
7This header file contains simple read/write macros for addressing
8the SDRAM, devices, GT`s internal registers and PCI (using the PCI`s address
9space). The macros take care of Big/Little endian conversions.
10*/
11
12#ifndef __INCcoreh
13#define __INCcoreh
14
15#include "mv_gen_reg.h"
16
17extern unsigned int INTERNAL_REG_BASE_ADDR;
18
19/****************************************/
20/* GENERAL Definitions */
21/****************************************/
22
23#define NO_BIT 0x00000000
24#define BIT0 0x00000001
25#define BIT1 0x00000002
26#define BIT2 0x00000004
27#define BIT3 0x00000008
28#define BIT4 0x00000010
29#define BIT5 0x00000020
30#define BIT6 0x00000040
31#define BIT7 0x00000080
32#define BIT8 0x00000100
33#define BIT9 0x00000200
34#define BIT10 0x00000400
35#define BIT11 0x00000800
36#define BIT12 0x00001000
37#define BIT13 0x00002000
38#define BIT14 0x00004000
39#define BIT15 0x00008000
40#define BIT16 0x00010000
41#define BIT17 0x00020000
42#define BIT18 0x00040000
43#define BIT19 0x00080000
44#define BIT20 0x00100000
45#define BIT21 0x00200000
46#define BIT22 0x00400000
47#define BIT23 0x00800000
48#define BIT24 0x01000000
49#define BIT25 0x02000000
50#define BIT26 0x04000000
51#define BIT27 0x08000000
52#define BIT28 0x10000000
53#define BIT29 0x20000000
54#define BIT30 0x40000000
55#define BIT31 0x80000000
56
57#define _1K 0x00000400
58#define _2K 0x00000800
59#define _4K 0x00001000
60#define _8K 0x00002000
61#define _16K 0x00004000
62#define _32K 0x00008000
63#define _64K 0x00010000
64#define _128K 0x00020000
65#define _256K 0x00040000
66#define _512K 0x00080000
67
68#define _1M 0x00100000
69#define _2M 0x00200000
70#define _3M 0x00300000
71#define _4M 0x00400000
72#define _5M 0x00500000
73#define _6M 0x00600000
74#define _7M 0x00700000
75#define _8M 0x00800000
76#define _9M 0x00900000
77#define _10M 0x00a00000
78#define _11M 0x00b00000
79#define _12M 0x00c00000
80#define _13M 0x00d00000
81#define _14M 0x00e00000
82#define _15M 0x00f00000
83#define _16M 0x01000000
84
85#define _32M 0x02000000
86#define _64M 0x04000000
87#define _128M 0x08000000
88#define _256M 0x10000000
89#define _512M 0x20000000
90
91#define _1G 0x40000000
92#define _2G 0x80000000
93
wdenk5da7f2f2004-01-03 00:43:19 +0000[diff] [blame]94/* Little to Big endian conversion macros */
95
96#ifdef LE /* Little Endian */
97#define SHORT_SWAP(X) (X)
98#define WORD_SWAP(X) (X)
99#define LONG_SWAP(X) ((l64)(X))
100
101#else /* Big Endian */
102#define SHORT_SWAP(X) ((X <<8 ) | (X >> 8))
103
104#define WORD_SWAP(X) (((X)&0xff)<<24)+ \
105 (((X)&0xff00)<<8)+ \
106 (((X)&0xff0000)>>8)+ \
107 (((X)&0xff000000)>>24)
108
109#define LONG_SWAP(X) ( (l64) (((X)&0xffULL)<<56)+ \
110 (((X)&0xff00ULL)<<40)+ \
111 (((X)&0xff0000ULL)<<24)+ \
112 (((X)&0xff000000ULL)<<8)+ \
113 (((X)&0xff00000000ULL)>>8)+ \
114 (((X)&0xff0000000000ULL)>>24)+ \
115 (((X)&0xff000000000000ULL)>>40)+ \
116 (((X)&0xff00000000000000ULL)>>56))
117
118#endif
119
120#ifndef NULL
121#define NULL 0
122#endif
123
124/* Those two definitions were defined to be compatible with MIPS */
125#define NONE_CACHEABLE 0x00000000
126#define CACHEABLE 0x00000000
127
128/* 750 cache line */
129#define CACHE_LINE_SIZE 32
130#define CACHELINE_MASK_BITS (CACHE_LINE_SIZE - 1)
131#define CACHELINE_ROUNDUP(A) (((A)+CACHELINE_MASK_BITS) & ~CACHELINE_MASK_BITS)
132
133/* Read/Write to/from GT`s internal registers */
134#define GT_REG_READ(offset, pData) \
135*pData = ( *((volatile unsigned int *)(NONE_CACHEABLE | \
136 INTERNAL_REG_BASE_ADDR | (offset))) ) ; \
137*pData = WORD_SWAP(*pData)
138
139#define GTREGREAD(offset) \
140 (WORD_SWAP( *((volatile unsigned int *)(NONE_CACHEABLE | \
141 INTERNAL_REG_BASE_ADDR | (offset))) ))
142
143#define GT_REG_WRITE(offset, data) \
144*((unsigned int *)( INTERNAL_REG_BASE_ADDR | (offset))) = \
145 WORD_SWAP(data)
146
147/* Write 32/16/8 bit */
148#define WRITE_CHAR(address, data) \
149 *((unsigned char *)(address)) = data
150#define WRITE_SHORT(address, data) \
151 *((unsigned short *)(address)) = data
152#define WRITE_WORD(address, data) \
153 *((unsigned int *)(address)) = data
154
155#define GT_WRITE_CHAR(address, data) WRITE_CHAR(address, data)
156
157/* Write 32/16/8 bit NonCacheable */
158/*
159#define GT_WRITE_CHAR(address, data) \
160 (*((unsigned char *)NONE_CACHEABLE(address))) = data
161#define GT_WRITE_SHORT(address, data) \
162 (*((unsigned short *)NONE_CACHEABLE(address))) = data
163#define GT_WRITE_WORD(address, data) \
164 (*((unsigned int *)NONE_CACHEABLE(address))) = data
165*/
166 /*#define GT_WRITE_CHAR(address, data) ((*((volatile unsigned char *)NONE_CACHEABLE((address)))) = ((unsigned char)(data)))1 */
167
168 /*#define GT_WRITE_SHORT(address, data) ((*((volatile unsigned short *)NONE_CACHEABLE((address)))) = ((unsigned short)(data)))1 */
169
170 /*#define GT_WRITE_WORD(address, data) ((*((volatile unsigned int *)NONE_CACHEABLE((address)))) = ((unsigned int)(data)))1 */
171
172
173/* Read 32/16/8 bits - returns data in variable. */
174#define READ_CHAR(address, pData) \
175 *pData = *((volatile unsigned char *)(address))
176
177#define READ_SHORT(address, pData) \
178 *pData = *((volatile unsigned short *)(address))
179
180#define READ_WORD(address, pData) \
181 *pData = *((volatile unsigned int *)(address))
182
183/* Read 32/16/8 bit - returns data direct. */
184#define READCHAR(address) \
185 *((volatile unsigned char *)((address) | NONE_CACHEABLE))
186
187#define READSHORT(address) \
188 *((volatile unsigned short *)((address) | NONE_CACHEABLE))
189
190#define READWORD(address) \
191 *((volatile unsigned int *)((address) | NONE_CACHEABLE))
192
193/* Those two Macros were defined to be compatible with MIPS */
194#define VIRTUAL_TO_PHY(x) (((unsigned int)x) & 0xffffffff)
195#define PHY_TO_VIRTUAL(x) (((unsigned int)x) | NONE_CACHEABLE)
196
197/* SET_REG_BITS(regOffset,bits) -
198 gets register offset and bits: a 32bit value. It set to logic '1' in the
199 internal register the bits which given as an input example:
200 SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
201 '1' in register 0x840 while the other bits stays as is. */
202#define SET_REG_BITS(regOffset,bits) \
203 *(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR | \
204 regOffset) |= (unsigned int)WORD_SWAP(bits)
205
206/* RESET_REG_BITS(regOffset,bits) -
207 gets register offset and bits: a 32bit value. It set to logic '0' in the
208 internal register the bits which given as an input example:
209 RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
210 '0' in register 0x840 while the other bits stays as is. */
211#define RESET_REG_BITS(regOffset,bits) \
212 *(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR \
213 | regOffset) &= ~( (unsigned int)WORD_SWAP(bits) )
214/* gets register offset and bits: a 32bit value. It set to logic '1' in the
215 internal register the bits which given as an input example:
216 GT_SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
217 '1' in register 0x840 while the other bits stays as is. */
218 /*#define GT_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)(NONE_CACHEABLE(INTERNAL_REG_BASE_ADDR) | (regOffset)))) |= ((unsigned int)WORD_SWAP(bits)))1 */
219 /*#define GT_SET_REG_BITS(regOffset,bits) RESET_REG_BITS(regOffset,bits)1 */
220#define GT_SET_REG_BITS(regOffset,bits) SET_REG_BITS(regOffset,bits)
221/* gets register offset and bits: a 32bit value. It set to logic '0' in the
222 internal register the bits which given as an input example:
223 GT_RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to
224 logic '0' in register 0x840 while the other bits stays as is. */
225 /*#define GT_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)(NONE_CACHEABLE(INTERNAL_REG_BASE_ADDR) | (regOffset)))) &= ~((unsigned int)WORD_SWAP(bits)))1 */
226#define GT_RESET_REG_BITS(regOffset,bits) RESET_REG_BITS(regOffset,bits)
227
228
229#define DEBUG_LED0_ON() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x8000,0)
230#define DEBUG_LED1_ON() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0xc000,0)
231#define DEBUG_LED2_ON() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x10000,0)
232#define DEBUG_LED0_OFF() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x14000,0)
233#define DEBUG_LED1_OFF() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x18000,0)
234#define DEBUG_LED2_OFF() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x1c000,0)
235
236#endif /* __INCcoreh */