blob: f07669374d703673a4961a22c8bcf9ef99bf497f [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Anton Schubert98530e92015-08-11 11:54:01 +02002/*
3 * PCIe driver for Marvell MVEBU SoCs
4 *
5 * Based on Barebox drivers/pci/pci-mvebu.c
6 *
7 * Ported to U-Boot by:
8 * Anton Schubert <anton.schubert@gmx.de>
9 * Stefan Roese <sr@denx.de>
Pali Rohár028ac882021-12-16 12:04:06 +010010 * Pali Rohár <pali@kernel.org>
Anton Schubert98530e92015-08-11 11:54:01 +020011 */
12
13#include <common.h>
Stefan Roese3179ec62019-01-25 11:52:43 +010014#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -060015#include <log.h>
Simon Glass9bc15642020-02-03 07:36:16 -070016#include <malloc.h>
Stefan Roese3179ec62019-01-25 11:52:43 +010017#include <dm/device-internal.h>
18#include <dm/lists.h>
19#include <dm/of_access.h>
Anton Schubert98530e92015-08-11 11:54:01 +020020#include <pci.h>
Pali Rohár5fc93e22021-12-21 12:20:19 +010021#include <reset.h>
Anton Schubert98530e92015-08-11 11:54:01 +020022#include <asm/io.h>
23#include <asm/arch/cpu.h>
24#include <asm/arch/soc.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060025#include <linux/bitops.h>
Pali Rohár91d02fb2021-12-21 12:20:17 +010026#include <linux/delay.h>
Stefan Roese3179ec62019-01-25 11:52:43 +010027#include <linux/errno.h>
28#include <linux/ioport.h>
Anton Schubert98530e92015-08-11 11:54:01 +020029#include <linux/mbus.h>
Pali Rohárca69af42021-12-21 12:20:13 +010030#include <linux/sizes.h>
Anton Schubert98530e92015-08-11 11:54:01 +020031
Anton Schubert98530e92015-08-11 11:54:01 +020032/* PCIe unit register offsets */
Pali Rohár13079172022-02-18 12:25:23 +010033#define MVPCIE_ROOT_PORT_PCI_CFG_OFF 0x0000
34#define MVPCIE_ROOT_PORT_PCI_EXP_OFF 0x0060
35#define MVPCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
36#define MVPCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
37#define MVPCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
38#define MVPCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
39#define MVPCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
40#define MVPCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
41#define MVPCIE_WIN5_CTRL_OFF 0x1880
42#define MVPCIE_WIN5_BASE_OFF 0x1884
43#define MVPCIE_WIN5_REMAP_OFF 0x188c
44#define MVPCIE_CONF_ADDR_OFF 0x18f8
45#define MVPCIE_CONF_DATA_OFF 0x18fc
46#define MVPCIE_CTRL_OFF 0x1a00
47#define MVPCIE_CTRL_RC_MODE BIT(1)
48#define MVPCIE_STAT_OFF 0x1a04
49#define MVPCIE_STAT_BUS (0xff << 8)
50#define MVPCIE_STAT_DEV (0x1f << 16)
51#define MVPCIE_STAT_LINK_DOWN BIT(0)
Anton Schubert98530e92015-08-11 11:54:01 +020052
Pali Rohár91d02fb2021-12-21 12:20:17 +010053#define LINK_WAIT_RETRIES 100
54#define LINK_WAIT_TIMEOUT 1000
55
Anton Schubert98530e92015-08-11 11:54:01 +020056struct mvebu_pcie {
57 struct pci_controller hose;
Anton Schubert98530e92015-08-11 11:54:01 +020058 void __iomem *base;
59 void __iomem *membase;
60 struct resource mem;
61 void __iomem *iobase;
Phil Sutter09577aa2021-01-03 23:06:46 +010062 struct resource io;
Pali Rohárbb26c4a2021-12-21 12:20:15 +010063 u32 intregs;
Anton Schubert98530e92015-08-11 11:54:01 +020064 u32 port;
65 u32 lane;
Pali Rohár5fc93e22021-12-21 12:20:19 +010066 bool is_x4;
Stefan Roese3179ec62019-01-25 11:52:43 +010067 int devfn;
Pali Rohár9e2274d2021-10-22 16:22:10 +020068 int sec_busno;
Stefan Roese3179ec62019-01-25 11:52:43 +010069 char name[16];
70 unsigned int mem_target;
71 unsigned int mem_attr;
Phil Sutter09577aa2021-01-03 23:06:46 +010072 unsigned int io_target;
73 unsigned int io_attr;
Pali Rohár31667222021-11-11 16:35:45 +010074 u32 cfgcache[(0x3c - 0x10) / 4];
Anton Schubert98530e92015-08-11 11:54:01 +020075};
76
Anton Schubert98530e92015-08-11 11:54:01 +020077static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie)
78{
79 u32 val;
Pali Rohár13079172022-02-18 12:25:23 +010080 val = readl(pcie->base + MVPCIE_STAT_OFF);
81 return !(val & MVPCIE_STAT_LINK_DOWN);
Anton Schubert98530e92015-08-11 11:54:01 +020082}
83
Pali Rohár91d02fb2021-12-21 12:20:17 +010084static void mvebu_pcie_wait_for_link(struct mvebu_pcie *pcie)
85{
86 int retries;
87
88 /* check if the link is up or not */
89 for (retries = 0; retries < LINK_WAIT_RETRIES; retries++) {
90 if (mvebu_pcie_link_up(pcie)) {
91 printf("%s: Link up\n", pcie->name);
92 return;
93 }
94
95 udelay(LINK_WAIT_TIMEOUT);
96 }
97
98 printf("%s: Link down\n", pcie->name);
99}
100
Anton Schubert98530e92015-08-11 11:54:01 +0200101static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie *pcie, int busno)
102{
103 u32 stat;
104
Pali Rohár13079172022-02-18 12:25:23 +0100105 stat = readl(pcie->base + MVPCIE_STAT_OFF);
106 stat &= ~MVPCIE_STAT_BUS;
Anton Schubert98530e92015-08-11 11:54:01 +0200107 stat |= busno << 8;
Pali Rohár13079172022-02-18 12:25:23 +0100108 writel(stat, pcie->base + MVPCIE_STAT_OFF);
Anton Schubert98530e92015-08-11 11:54:01 +0200109}
110
111static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie *pcie, int devno)
112{
113 u32 stat;
114
Pali Rohár13079172022-02-18 12:25:23 +0100115 stat = readl(pcie->base + MVPCIE_STAT_OFF);
116 stat &= ~MVPCIE_STAT_DEV;
Anton Schubert98530e92015-08-11 11:54:01 +0200117 stat |= devno << 16;
Pali Rohár13079172022-02-18 12:25:23 +0100118 writel(stat, pcie->base + MVPCIE_STAT_OFF);
Anton Schubert98530e92015-08-11 11:54:01 +0200119}
120
Anton Schubert98530e92015-08-11 11:54:01 +0200121static inline struct mvebu_pcie *hose_to_pcie(struct pci_controller *hose)
122{
123 return container_of(hose, struct mvebu_pcie, hose);
124}
125
Pali Rohár9e2274d2021-10-22 16:22:10 +0200126static bool mvebu_pcie_valid_addr(struct mvebu_pcie *pcie,
127 int busno, int dev, int func)
Marek Behún89036732021-02-08 23:01:40 +0100128{
Pali Rohár0ef79052022-02-15 11:34:01 +0100129 /* On the root bus is only one PCI Bridge */
130 if (busno == 0 && (dev != 0 || func != 0))
Pali Rohár9e2274d2021-10-22 16:22:10 +0200131 return false;
Marek Behún89036732021-02-08 23:01:40 +0100132
Pali Rohár2f9b5192021-10-22 16:22:12 +0200133 /* Access to other buses is possible when link is up */
Pali Rohár0ef79052022-02-15 11:34:01 +0100134 if (busno != 0 && !mvebu_pcie_link_up(pcie))
Pali Rohár2f9b5192021-10-22 16:22:12 +0200135 return false;
136
Pali Rohár9e2274d2021-10-22 16:22:10 +0200137 /* On secondary bus can be only one PCIe device */
138 if (busno == pcie->sec_busno && dev != 0)
139 return false;
140
141 return true;
Marek Behún89036732021-02-08 23:01:40 +0100142}
143
Simon Glass2a311e82020-01-27 08:49:37 -0700144static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
Stefan Roese3179ec62019-01-25 11:52:43 +0100145 uint offset, ulong *valuep,
146 enum pci_size_t size)
Anton Schubert98530e92015-08-11 11:54:01 +0200147{
Simon Glassfa20e932020-12-03 16:55:20 -0700148 struct mvebu_pcie *pcie = dev_get_plat(bus);
Pali Rohár9e2274d2021-10-22 16:22:10 +0200149 int busno = PCI_BUS(bdf) - dev_seq(bus);
150 u32 addr, data;
Stefan Roese3179ec62019-01-25 11:52:43 +0100151
Marek Behún89036732021-02-08 23:01:40 +0100152 debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
153 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
Anton Schubert98530e92015-08-11 11:54:01 +0200154
Pali Rohár9e2274d2021-10-22 16:22:10 +0200155 if (!mvebu_pcie_valid_addr(pcie, busno, PCI_DEV(bdf), PCI_FUNC(bdf))) {
Stefan Roese8d77b0a2021-01-25 15:25:31 +0100156 debug("- out of range\n");
157 *valuep = pci_get_ff(size);
158 return 0;
159 }
160
Pali Rohár9e2274d2021-10-22 16:22:10 +0200161 /*
Pali Rohár0ef79052022-02-15 11:34:01 +0100162 * The configuration space of the PCI Bridge on the root bus (zero) is
Pali Rohár31667222021-11-11 16:35:45 +0100163 * of Type 0 but the BAR registers (including ROM BAR) don't have the
164 * same meaning as in the PCIe specification. Therefore do not access
165 * BAR registers and non-common registers (those which have different
166 * meaning for Type 0 and Type 1 config space) of the PCI Bridge and
167 * instead read their content from driver virtual cfgcache[].
Pali Rohár9e2274d2021-10-22 16:22:10 +0200168 */
Pali Rohár0ef79052022-02-15 11:34:01 +0100169 if (busno == 0 && ((offset >= 0x10 && offset < 0x34) ||
170 (offset >= 0x38 && offset < 0x3c))) {
Pali Rohár9e2274d2021-10-22 16:22:10 +0200171 data = pcie->cfgcache[(offset - 0x10) / 4];
172 debug("(addr,size,val)=(0x%04x, %d, 0x%08x) from cfgcache\n",
173 offset, size, data);
174 *valuep = pci_conv_32_to_size(data, offset, size);
175 return 0;
Pali Rohár9e2274d2021-10-22 16:22:10 +0200176 }
177
178 /*
Pali Rohár0ef79052022-02-15 11:34:01 +0100179 * PCI bridge is device 0 at the root bus (zero) but mvebu has it
180 * mapped on secondary bus with device number 1.
Pali Rohár9e2274d2021-10-22 16:22:10 +0200181 */
Pali Rohár0ef79052022-02-15 11:34:01 +0100182 if (busno == 0)
Pali Rohár43a9fc72021-11-26 11:42:45 +0100183 addr = PCI_CONF1_EXT_ADDRESS(pcie->sec_busno, 1, 0, offset);
Pali Rohár9e2274d2021-10-22 16:22:10 +0200184 else
Pali Rohár43a9fc72021-11-26 11:42:45 +0100185 addr = PCI_CONF1_EXT_ADDRESS(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset);
Pali Rohár9e2274d2021-10-22 16:22:10 +0200186
Anton Schubert98530e92015-08-11 11:54:01 +0200187 /* write address */
Pali Rohár13079172022-02-18 12:25:23 +0100188 writel(addr, pcie->base + MVPCIE_CONF_ADDR_OFF);
Marek Behún9df558d2021-02-08 23:01:38 +0100189
190 /* read data */
Pali Rohár89220132021-10-22 16:22:09 +0200191 switch (size) {
192 case PCI_SIZE_8:
Pali Rohár13079172022-02-18 12:25:23 +0100193 data = readb(pcie->base + MVPCIE_CONF_DATA_OFF + (offset & 3));
Pali Rohár89220132021-10-22 16:22:09 +0200194 break;
195 case PCI_SIZE_16:
Pali Rohár13079172022-02-18 12:25:23 +0100196 data = readw(pcie->base + MVPCIE_CONF_DATA_OFF + (offset & 2));
Pali Rohár89220132021-10-22 16:22:09 +0200197 break;
198 case PCI_SIZE_32:
Pali Rohár13079172022-02-18 12:25:23 +0100199 data = readl(pcie->base + MVPCIE_CONF_DATA_OFF);
Pali Rohár89220132021-10-22 16:22:09 +0200200 break;
201 default:
202 return -EINVAL;
203 }
204
Pali Rohár0ef79052022-02-15 11:34:01 +0100205 if (busno == 0 && (offset & ~3) == (PCI_HEADER_TYPE & ~3)) {
Pali Rohár9e2274d2021-10-22 16:22:10 +0200206 /*
207 * Change Header Type of PCI Bridge device to Type 1
208 * (0x01, used by PCI Bridges) because mvebu reports
209 * Type 0 (0x00, used by Upstream and Endpoint devices).
210 */
211 data = pci_conv_size_to_32(data, 0, offset, size);
212 data &= ~0x007f0000;
213 data |= PCI_HEADER_TYPE_BRIDGE << 16;
214 data = pci_conv_32_to_size(data, offset, size);
215 }
216
Marek Behúnd2ed1e52021-02-08 23:01:39 +0100217 debug("(addr,size,val)=(0x%04x, %d, 0x%08x)\n", offset, size, data);
Pali Rohár89220132021-10-22 16:22:09 +0200218 *valuep = data;
Anton Schubert98530e92015-08-11 11:54:01 +0200219
220 return 0;
221}
222
Stefan Roese3179ec62019-01-25 11:52:43 +0100223static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
224 uint offset, ulong value,
225 enum pci_size_t size)
Anton Schubert98530e92015-08-11 11:54:01 +0200226{
Simon Glassfa20e932020-12-03 16:55:20 -0700227 struct mvebu_pcie *pcie = dev_get_plat(bus);
Pali Rohár9e2274d2021-10-22 16:22:10 +0200228 int busno = PCI_BUS(bdf) - dev_seq(bus);
229 u32 addr, data;
Stefan Roese3179ec62019-01-25 11:52:43 +0100230
Marek Behún89036732021-02-08 23:01:40 +0100231 debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
232 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
Marek Behúnd2ed1e52021-02-08 23:01:39 +0100233 debug("(addr,size,val)=(0x%04x, %d, 0x%08lx)\n", offset, size, value);
Anton Schubert98530e92015-08-11 11:54:01 +0200234
Pali Rohár9e2274d2021-10-22 16:22:10 +0200235 if (!mvebu_pcie_valid_addr(pcie, busno, PCI_DEV(bdf), PCI_FUNC(bdf))) {
Stefan Roese8d77b0a2021-01-25 15:25:31 +0100236 debug("- out of range\n");
237 return 0;
Pali Rohár9e2274d2021-10-22 16:22:10 +0200238 }
239
240 /*
Pali Rohár31667222021-11-11 16:35:45 +0100241 * As explained in mvebu_pcie_read_config(), PCI Bridge Type 1 specific
242 * config registers are not available, so we write their content only
243 * into driver virtual cfgcache[].
244 * And as explained in mvebu_pcie_probe(), mvebu has its own specific
Pali Rohár0ef79052022-02-15 11:34:01 +0100245 * way for configuring secondary bus number.
Pali Rohár9e2274d2021-10-22 16:22:10 +0200246 */
Pali Rohár0ef79052022-02-15 11:34:01 +0100247 if (busno == 0 && ((offset >= 0x10 && offset < 0x34) ||
248 (offset >= 0x38 && offset < 0x3c))) {
Pali Rohár9e2274d2021-10-22 16:22:10 +0200249 debug("Writing to cfgcache only\n");
250 data = pcie->cfgcache[(offset - 0x10) / 4];
251 data = pci_conv_size_to_32(data, value, offset, size);
252 /* mvebu PCI bridge does not have configurable bars */
253 if ((offset & ~3) == PCI_BASE_ADDRESS_0 ||
Pali Rohár31667222021-11-11 16:35:45 +0100254 (offset & ~3) == PCI_BASE_ADDRESS_1 ||
255 (offset & ~3) == PCI_ROM_ADDRESS1)
Pali Rohár9e2274d2021-10-22 16:22:10 +0200256 data = 0x0;
257 pcie->cfgcache[(offset - 0x10) / 4] = data;
Pali Rohár9e2274d2021-10-22 16:22:10 +0200258 /* mvebu has its own way how to set PCI secondary bus number */
259 if (offset == PCI_SECONDARY_BUS ||
260 (offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8)) {
261 pcie->sec_busno = (data >> 8) & 0xff;
262 mvebu_pcie_set_local_bus_nr(pcie, pcie->sec_busno);
263 debug("Secondary bus number was changed to %d\n",
264 pcie->sec_busno);
265 }
266 return 0;
Anton Schubert98530e92015-08-11 11:54:01 +0200267 }
268
Pali Rohár9e2274d2021-10-22 16:22:10 +0200269 /*
Pali Rohár0ef79052022-02-15 11:34:01 +0100270 * PCI bridge is device 0 at the root bus (zero) but mvebu has it
271 * mapped on secondary bus with device number 1.
Pali Rohár9e2274d2021-10-22 16:22:10 +0200272 */
Pali Rohár0ef79052022-02-15 11:34:01 +0100273 if (busno == 0)
Pali Rohár43a9fc72021-11-26 11:42:45 +0100274 addr = PCI_CONF1_EXT_ADDRESS(pcie->sec_busno, 1, 0, offset);
Pali Rohár9e2274d2021-10-22 16:22:10 +0200275 else
Pali Rohár43a9fc72021-11-26 11:42:45 +0100276 addr = PCI_CONF1_EXT_ADDRESS(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset);
Pali Rohár9e2274d2021-10-22 16:22:10 +0200277
Marek Behún9df558d2021-02-08 23:01:38 +0100278 /* write address */
Pali Rohár13079172022-02-18 12:25:23 +0100279 writel(addr, pcie->base + MVPCIE_CONF_ADDR_OFF);
Marek Behún9df558d2021-02-08 23:01:38 +0100280
281 /* write data */
Pali Rohár35bce492021-10-22 16:22:08 +0200282 switch (size) {
283 case PCI_SIZE_8:
Pali Rohár13079172022-02-18 12:25:23 +0100284 writeb(value, pcie->base + MVPCIE_CONF_DATA_OFF + (offset & 3));
Pali Rohár35bce492021-10-22 16:22:08 +0200285 break;
286 case PCI_SIZE_16:
Pali Rohár13079172022-02-18 12:25:23 +0100287 writew(value, pcie->base + MVPCIE_CONF_DATA_OFF + (offset & 2));
Pali Rohár35bce492021-10-22 16:22:08 +0200288 break;
289 case PCI_SIZE_32:
Pali Rohár13079172022-02-18 12:25:23 +0100290 writel(value, pcie->base + MVPCIE_CONF_DATA_OFF);
Pali Rohár35bce492021-10-22 16:22:08 +0200291 break;
292 default:
293 return -EINVAL;
294 }
Anton Schubert98530e92015-08-11 11:54:01 +0200295
296 return 0;
297}
298
299/*
300 * Setup PCIE BARs and Address Decode Wins:
Pali Rohár495f3132021-11-11 16:35:42 +0100301 * BAR[0] -> internal registers
302 * BAR[1] -> covers all DRAM banks
303 * BAR[2] -> disabled
Anton Schubert98530e92015-08-11 11:54:01 +0200304 * WIN[0-3] -> DRAM bank[0-3]
305 */
306static void mvebu_pcie_setup_wins(struct mvebu_pcie *pcie)
307{
308 const struct mbus_dram_target_info *dram = mvebu_mbus_dram_info();
309 u32 size;
310 int i;
311
312 /* First, disable and clear BARs and windows. */
313 for (i = 1; i < 3; i++) {
Pali Rohár13079172022-02-18 12:25:23 +0100314 writel(0, pcie->base + MVPCIE_BAR_CTRL_OFF(i));
315 writel(0, pcie->base + MVPCIE_BAR_LO_OFF(i));
316 writel(0, pcie->base + MVPCIE_BAR_HI_OFF(i));
Anton Schubert98530e92015-08-11 11:54:01 +0200317 }
318
319 for (i = 0; i < 5; i++) {
Pali Rohár13079172022-02-18 12:25:23 +0100320 writel(0, pcie->base + MVPCIE_WIN04_CTRL_OFF(i));
321 writel(0, pcie->base + MVPCIE_WIN04_BASE_OFF(i));
322 writel(0, pcie->base + MVPCIE_WIN04_REMAP_OFF(i));
Anton Schubert98530e92015-08-11 11:54:01 +0200323 }
324
Pali Rohár13079172022-02-18 12:25:23 +0100325 writel(0, pcie->base + MVPCIE_WIN5_CTRL_OFF);
326 writel(0, pcie->base + MVPCIE_WIN5_BASE_OFF);
327 writel(0, pcie->base + MVPCIE_WIN5_REMAP_OFF);
Anton Schubert98530e92015-08-11 11:54:01 +0200328
329 /* Setup windows for DDR banks. Count total DDR size on the fly. */
330 size = 0;
331 for (i = 0; i < dram->num_cs; i++) {
332 const struct mbus_dram_window *cs = dram->cs + i;
333
334 writel(cs->base & 0xffff0000,
Pali Rohár13079172022-02-18 12:25:23 +0100335 pcie->base + MVPCIE_WIN04_BASE_OFF(i));
336 writel(0, pcie->base + MVPCIE_WIN04_REMAP_OFF(i));
Anton Schubert98530e92015-08-11 11:54:01 +0200337 writel(((cs->size - 1) & 0xffff0000) |
338 (cs->mbus_attr << 8) |
339 (dram->mbus_dram_target_id << 4) | 1,
Pali Rohár13079172022-02-18 12:25:23 +0100340 pcie->base + MVPCIE_WIN04_CTRL_OFF(i));
Anton Schubert98530e92015-08-11 11:54:01 +0200341
342 size += cs->size;
343 }
344
345 /* Round up 'size' to the nearest power of two. */
346 if ((size & (size - 1)) != 0)
347 size = 1 << fls(size);
348
349 /* Setup BAR[1] to all DRAM banks. */
Pali Rohár13079172022-02-18 12:25:23 +0100350 writel(dram->cs[0].base | 0xc, pcie->base + MVPCIE_BAR_LO_OFF(1));
351 writel(0, pcie->base + MVPCIE_BAR_HI_OFF(1));
Anton Schubert98530e92015-08-11 11:54:01 +0200352 writel(((size - 1) & 0xffff0000) | 0x1,
Pali Rohár13079172022-02-18 12:25:23 +0100353 pcie->base + MVPCIE_BAR_CTRL_OFF(1));
Pali Rohár495f3132021-11-11 16:35:42 +0100354
355 /* Setup BAR[0] to internal registers. */
Pali Rohár13079172022-02-18 12:25:23 +0100356 writel(pcie->intregs, pcie->base + MVPCIE_BAR_LO_OFF(0));
357 writel(0, pcie->base + MVPCIE_BAR_HI_OFF(0));
Anton Schubert98530e92015-08-11 11:54:01 +0200358}
359
Pali Rohár3f6890d2021-12-21 12:20:16 +0100360/* Only enable PCIe link, do not setup it */
361static int mvebu_pcie_enable_link(struct mvebu_pcie *pcie, ofnode node)
Anton Schubert98530e92015-08-11 11:54:01 +0200362{
Pali Rohár5fc93e22021-12-21 12:20:19 +0100363 struct reset_ctl rst;
364 int ret;
365
366 ret = reset_get_by_index_nodev(node, 0, &rst);
367 if (ret == -ENOENT) {
368 return 0;
369 } else if (ret < 0) {
370 printf("%s: cannot get reset controller: %d\n", pcie->name, ret);
371 return ret;
372 }
373
374 ret = reset_request(&rst);
375 if (ret) {
376 printf("%s: cannot request reset controller: %d\n", pcie->name, ret);
377 return ret;
378 }
379
380 ret = reset_deassert(&rst);
381 reset_free(&rst);
382 if (ret) {
383 printf("%s: cannot enable PCIe port: %d\n", pcie->name, ret);
384 return ret;
385 }
386
Pali Rohár3f6890d2021-12-21 12:20:16 +0100387 return 0;
388}
389
390/* Setup PCIe link but do not enable it */
391static void mvebu_pcie_setup_link(struct mvebu_pcie *pcie)
392{
Anton Schubert98530e92015-08-11 11:54:01 +0200393 u32 reg;
Anton Schubert98530e92015-08-11 11:54:01 +0200394
Pali Rohár6f3e57a2021-10-22 16:22:14 +0200395 /* Setup PCIe controller to Root Complex mode */
Pali Rohár13079172022-02-18 12:25:23 +0100396 reg = readl(pcie->base + MVPCIE_CTRL_OFF);
397 reg |= MVPCIE_CTRL_RC_MODE;
398 writel(reg, pcie->base + MVPCIE_CTRL_OFF);
Pali Rohár5fc93e22021-12-21 12:20:19 +0100399
400 /*
401 * Set Maximum Link Width to X1 or X4 in Root Port's PCIe Link
402 * Capability register. This register is defined by PCIe specification
403 * as read-only but this mvebu controller has it as read-write and must
404 * be set to number of SerDes PCIe lanes (1 or 4). If this register is
405 * not set correctly then link with endpoint card is not established.
406 */
Pali Rohár13079172022-02-18 12:25:23 +0100407 reg = readl(pcie->base + MVPCIE_ROOT_PORT_PCI_EXP_OFF + PCI_EXP_LNKCAP);
Pali Rohár5fc93e22021-12-21 12:20:19 +0100408 reg &= ~PCI_EXP_LNKCAP_MLW;
409 reg |= (pcie->is_x4 ? 4 : 1) << 4;
Pali Rohár13079172022-02-18 12:25:23 +0100410 writel(reg, pcie->base + MVPCIE_ROOT_PORT_PCI_EXP_OFF + PCI_EXP_LNKCAP);
Pali Rohár3f6890d2021-12-21 12:20:16 +0100411}
412
413static int mvebu_pcie_probe(struct udevice *dev)
414{
415 struct mvebu_pcie *pcie = dev_get_plat(dev);
416 struct udevice *ctlr = pci_get_controller(dev);
417 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
418 u32 reg;
Pali Rohár6f3e57a2021-10-22 16:22:14 +0200419
Pali Rohár9e2274d2021-10-22 16:22:10 +0200420 /*
421 * Change Class Code of PCI Bridge device to PCI Bridge (0x600400)
422 * because default value is Memory controller (0x508000) which
423 * U-Boot cannot recognize as P2P Bridge.
424 *
425 * Note that this mvebu PCI Bridge does not have compliant Type 1
Pali Rohár31667222021-11-11 16:35:45 +0100426 * Configuration Space. Header Type is reported as Type 0 and it
427 * has format of Type 0 config space.
428 *
429 * Moreover Type 0 BAR registers (ranges 0x10 - 0x28 and 0x30 - 0x34)
430 * have the same format in Marvell's specification as in PCIe
431 * specification, but their meaning is totally different and they do
432 * different things: they are aliased into internal mvebu registers
Pali Rohár13079172022-02-18 12:25:23 +0100433 * (e.g. MVPCIE_BAR_LO_OFF) and these should not be changed or
Pali Rohár31667222021-11-11 16:35:45 +0100434 * reconfigured by pci device drivers.
Pali Rohár9e2274d2021-10-22 16:22:10 +0200435 *
Pali Rohár31667222021-11-11 16:35:45 +0100436 * So our driver converts Type 0 config space to Type 1 and reports
437 * Header Type as Type 1. Access to BAR registers and to non-existent
438 * Type 1 registers is redirected to the virtual cfgcache[] buffer,
439 * which avoids changing unrelated registers.
Pali Rohár9e2274d2021-10-22 16:22:10 +0200440 */
Pali Rohár13079172022-02-18 12:25:23 +0100441 reg = readl(pcie->base + MVPCIE_ROOT_PORT_PCI_CFG_OFF + PCI_CLASS_REVISION);
Pali Rohár9e2274d2021-10-22 16:22:10 +0200442 reg &= ~0xffffff00;
443 reg |= (PCI_CLASS_BRIDGE_PCI << 8) << 8;
Pali Rohár13079172022-02-18 12:25:23 +0100444 writel(reg, pcie->base + MVPCIE_ROOT_PORT_PCI_CFG_OFF + PCI_CLASS_REVISION);
Marek Behún89036732021-02-08 23:01:40 +0100445
Pali Rohár9e2274d2021-10-22 16:22:10 +0200446 /*
447 * mvebu uses local bus number and local device number to determinate
448 * type of config request. Type 0 is used if target bus number equals
449 * local bus number and target device number differs from local device
450 * number. Type 1 is used if target bus number differs from local bus
451 * number. And when target bus number equals local bus number and
452 * target device equals local device number then request is routed to
453 * PCI Bridge which represent local PCIe Root Port.
454 *
Pali Rohár0ef79052022-02-15 11:34:01 +0100455 * It means that PCI root and secondary buses shares one bus number
Pali Rohár9e2274d2021-10-22 16:22:10 +0200456 * which is configured via local bus number. Determination if config
Pali Rohár0ef79052022-02-15 11:34:01 +0100457 * request should go to root or secondary bus is done based on local
Pali Rohár9e2274d2021-10-22 16:22:10 +0200458 * device number.
459 *
460 * PCIe is point-to-point bus, so at secondary bus is always exactly one
461 * device with number 0. So set local device number to 1, it would not
462 * conflict with any device on secondary bus number and will ensure that
463 * accessing secondary bus and all buses behind secondary would work
464 * automatically and correctly. Therefore this configuration of local
465 * device number implies that setting of local bus number configures
466 * secondary bus number. Set it to 0 as U-Boot CONFIG_PCI_PNP code will
467 * later configure it via config write requests to the correct value.
468 * mvebu_pcie_write_config() catches config write requests which tries
Pali Rohár0ef79052022-02-15 11:34:01 +0100469 * to change secondary bus number and correctly updates local bus number
470 * based on new secondary bus number.
Pali Rohár9e2274d2021-10-22 16:22:10 +0200471 *
472 * With this configuration is PCI Bridge available at secondary bus as
Pali Rohár0ef79052022-02-15 11:34:01 +0100473 * device number 1. But it must be available at root bus (zero) as device
Pali Rohár9e2274d2021-10-22 16:22:10 +0200474 * number 0. So in mvebu_pcie_read_config() and mvebu_pcie_write_config()
Pali Rohár0ef79052022-02-15 11:34:01 +0100475 * functions rewrite address to the real one when accessing the root bus.
Pali Rohár9e2274d2021-10-22 16:22:10 +0200476 */
477 mvebu_pcie_set_local_bus_nr(pcie, 0);
478 mvebu_pcie_set_local_dev_nr(pcie, 1);
Anton Schubert98530e92015-08-11 11:54:01 +0200479
Pali Roháred9bcb92022-01-13 14:28:04 +0100480 /*
481 * Kirkwood arch code already maps mbus windows for PCIe IO and MEM.
482 * So skip calling mvebu_mbus_add_window_by_id() function as it would
483 * fail on error "conflicts with another window" which means conflict
484 * with existing PCIe window mappings.
485 */
486#ifndef CONFIG_ARCH_KIRKWOOD
Pali Rohárca69af42021-12-21 12:20:13 +0100487 if (resource_size(&pcie->mem) &&
488 mvebu_mbus_add_window_by_id(pcie->mem_target, pcie->mem_attr,
Stefan Roese3179ec62019-01-25 11:52:43 +0100489 (phys_addr_t)pcie->mem.start,
Pali Rohár2aeb9422021-11-11 16:35:43 +0100490 resource_size(&pcie->mem))) {
Pali Rohár3f6890d2021-12-21 12:20:16 +0100491 printf("%s: unable to add mbus window for mem at %08x+%08x\n",
492 pcie->name,
Pali Rohár2aeb9422021-11-11 16:35:43 +0100493 (u32)pcie->mem.start, (unsigned)resource_size(&pcie->mem));
Pali Rohárca69af42021-12-21 12:20:13 +0100494 pcie->mem.start = 0;
495 pcie->mem.end = -1;
Stefan Roese3179ec62019-01-25 11:52:43 +0100496 }
497
Pali Rohárca69af42021-12-21 12:20:13 +0100498 if (resource_size(&pcie->io) &&
499 mvebu_mbus_add_window_by_id(pcie->io_target, pcie->io_attr,
Phil Sutter09577aa2021-01-03 23:06:46 +0100500 (phys_addr_t)pcie->io.start,
Pali Rohár2aeb9422021-11-11 16:35:43 +0100501 resource_size(&pcie->io))) {
Pali Rohár3f6890d2021-12-21 12:20:16 +0100502 printf("%s: unable to add mbus window for IO at %08x+%08x\n",
503 pcie->name,
Pali Rohár2aeb9422021-11-11 16:35:43 +0100504 (u32)pcie->io.start, (unsigned)resource_size(&pcie->io));
Pali Rohárca69af42021-12-21 12:20:13 +0100505 pcie->io.start = 0;
506 pcie->io.end = -1;
Phil Sutter09577aa2021-01-03 23:06:46 +0100507 }
Pali Roháred9bcb92022-01-13 14:28:04 +0100508#endif
Phil Sutter09577aa2021-01-03 23:06:46 +0100509
Stefan Roese3179ec62019-01-25 11:52:43 +0100510 /* Setup windows and configure host bridge */
511 mvebu_pcie_setup_wins(pcie);
512
Stefan Roese3179ec62019-01-25 11:52:43 +0100513 /* PCI memory space */
514 pci_set_region(hose->regions + 0, pcie->mem.start,
Pali Rohár2aeb9422021-11-11 16:35:43 +0100515 pcie->mem.start, resource_size(&pcie->mem), PCI_REGION_MEM);
Pali Rohárca69af42021-12-21 12:20:13 +0100516 hose->region_count = 1;
517
518 if (resource_size(&pcie->mem)) {
519 pci_set_region(hose->regions + hose->region_count,
520 pcie->mem.start, pcie->mem.start,
521 resource_size(&pcie->mem),
522 PCI_REGION_MEM);
523 hose->region_count++;
524 }
525
526 if (resource_size(&pcie->io)) {
527 pci_set_region(hose->regions + hose->region_count,
528 pcie->io.start, pcie->io.start,
529 resource_size(&pcie->io),
530 PCI_REGION_IO);
531 hose->region_count++;
532 }
Stefan Roese3179ec62019-01-25 11:52:43 +0100533
Pali Rohár9e2274d2021-10-22 16:22:10 +0200534 /* PCI Bridge support 32-bit I/O and 64-bit prefetch mem addressing */
535 pcie->cfgcache[(PCI_IO_BASE - 0x10) / 4] =
536 PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8);
537 pcie->cfgcache[(PCI_PREF_MEMORY_BASE - 0x10) / 4] =
538 PCI_PREF_RANGE_TYPE_64 | (PCI_PREF_RANGE_TYPE_64 << 16);
539
Pali Rohár91d02fb2021-12-21 12:20:17 +0100540 mvebu_pcie_wait_for_link(pcie);
541
Stefan Roese3179ec62019-01-25 11:52:43 +0100542 return 0;
543}
544
Stefan Roese3179ec62019-01-25 11:52:43 +0100545#define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
546#define DT_TYPE_IO 0x1
547#define DT_TYPE_MEM32 0x2
548#define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
549#define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
550
551static int mvebu_get_tgt_attr(ofnode node, int devfn,
552 unsigned long type,
553 unsigned int *tgt,
554 unsigned int *attr)
555{
556 const int na = 3, ns = 2;
557 const __be32 *range;
558 int rlen, nranges, rangesz, pna, i;
559
560 *tgt = -1;
561 *attr = -1;
562
563 range = ofnode_get_property(node, "ranges", &rlen);
564 if (!range)
565 return -EINVAL;
566
Stefan Roese24e23bd2019-02-11 07:53:34 +0100567 /*
568 * Linux uses of_n_addr_cells() to get the number of address cells
569 * here. Currently this function is only available in U-Boot when
570 * CONFIG_OF_LIVE is enabled. Until this is enabled for MVEBU in
571 * general, lets't hardcode the "pna" value in the U-Boot code.
572 */
Stefan Roese3179ec62019-01-25 11:52:43 +0100573 pna = 2; /* hardcoded for now because of lack of of_n_addr_cells() */
574 rangesz = pna + na + ns;
575 nranges = rlen / sizeof(__be32) / rangesz;
Anton Schubert98530e92015-08-11 11:54:01 +0200576
Stefan Roese3179ec62019-01-25 11:52:43 +0100577 for (i = 0; i < nranges; i++, range += rangesz) {
578 u32 flags = of_read_number(range, 1);
579 u32 slot = of_read_number(range + 1, 1);
580 u64 cpuaddr = of_read_number(range + na, pna);
581 unsigned long rtype;
Anton Schubert98530e92015-08-11 11:54:01 +0200582
Stefan Roese3179ec62019-01-25 11:52:43 +0100583 if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
584 rtype = IORESOURCE_IO;
585 else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
586 rtype = IORESOURCE_MEM;
587 else
Anton Schubert98530e92015-08-11 11:54:01 +0200588 continue;
Stefan Roese3179ec62019-01-25 11:52:43 +0100589
590 /*
591 * The Linux code used PCI_SLOT() here, which expects devfn
592 * in bits 7..0. PCI_DEV() in U-Boot is similar to PCI_SLOT(),
593 * only expects devfn in 15..8, where its saved in this driver.
594 */
595 if (slot == PCI_DEV(devfn) && type == rtype) {
596 *tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
597 *attr = DT_CPUADDR_TO_ATTR(cpuaddr);
598 return 0;
Anton Schubert98530e92015-08-11 11:54:01 +0200599 }
Stefan Roese3179ec62019-01-25 11:52:43 +0100600 }
Anton Schubert98530e92015-08-11 11:54:01 +0200601
Stefan Roese3179ec62019-01-25 11:52:43 +0100602 return -ENOENT;
603}
Anton Schubert98530e92015-08-11 11:54:01 +0200604
Pali Rohár3f6890d2021-12-21 12:20:16 +0100605static int mvebu_pcie_port_parse_dt(ofnode node, ofnode parent, struct mvebu_pcie *pcie)
Stefan Roese3179ec62019-01-25 11:52:43 +0100606{
Pali Rohár3f6890d2021-12-21 12:20:16 +0100607 struct fdt_pci_addr pci_addr;
Pali Rohár807292f2021-12-21 12:20:14 +0100608 const u32 *addr;
Pali Rohár5fc93e22021-12-21 12:20:19 +0100609 u32 num_lanes;
Stefan Roese3179ec62019-01-25 11:52:43 +0100610 int ret = 0;
Pali Rohár807292f2021-12-21 12:20:14 +0100611 int len;
Anton Schubert98530e92015-08-11 11:54:01 +0200612
Stefan Roese3179ec62019-01-25 11:52:43 +0100613 /* Get port number, lane number and memory target / attr */
Pali Rohár3f6890d2021-12-21 12:20:16 +0100614 if (ofnode_read_u32(node, "marvell,pcie-port",
Stefan Roese3179ec62019-01-25 11:52:43 +0100615 &pcie->port)) {
616 ret = -ENODEV;
617 goto err;
618 }
Anton Schubert98530e92015-08-11 11:54:01 +0200619
Pali Rohár3f6890d2021-12-21 12:20:16 +0100620 if (ofnode_read_u32(node, "marvell,pcie-lane", &pcie->lane))
Stefan Roese3179ec62019-01-25 11:52:43 +0100621 pcie->lane = 0;
Anton Schubert98530e92015-08-11 11:54:01 +0200622
Stefan Roese3179ec62019-01-25 11:52:43 +0100623 sprintf(pcie->name, "pcie%d.%d", pcie->port, pcie->lane);
Anton Schubert98530e92015-08-11 11:54:01 +0200624
Pali Rohár5fc93e22021-12-21 12:20:19 +0100625 if (!ofnode_read_u32(node, "num-lanes", &num_lanes) && num_lanes == 4)
626 pcie->is_x4 = true;
627
Pali Rohár3f6890d2021-12-21 12:20:16 +0100628 /* devfn is in bits [15:8], see PCI_DEV usage */
629 ret = ofnode_read_pci_addr(node, FDT_PCI_SPACE_CONFIG, "reg", &pci_addr);
630 if (ret < 0) {
631 printf("%s: property \"reg\" is invalid\n", pcie->name);
Stefan Roese3179ec62019-01-25 11:52:43 +0100632 goto err;
633 }
Pali Rohár3f6890d2021-12-21 12:20:16 +0100634 pcie->devfn = pci_addr.phys_hi & 0xff00;
Anton Schubert98530e92015-08-11 11:54:01 +0200635
Pali Rohár3f6890d2021-12-21 12:20:16 +0100636 ret = mvebu_get_tgt_attr(parent, pcie->devfn,
Stefan Roese3179ec62019-01-25 11:52:43 +0100637 IORESOURCE_MEM,
638 &pcie->mem_target, &pcie->mem_attr);
639 if (ret < 0) {
640 printf("%s: cannot get tgt/attr for mem window\n", pcie->name);
641 goto err;
642 }
Anton Schubert98530e92015-08-11 11:54:01 +0200643
Pali Rohár3f6890d2021-12-21 12:20:16 +0100644 ret = mvebu_get_tgt_attr(parent, pcie->devfn,
Phil Sutter09577aa2021-01-03 23:06:46 +0100645 IORESOURCE_IO,
646 &pcie->io_target, &pcie->io_attr);
647 if (ret < 0) {
648 printf("%s: cannot get tgt/attr for IO window\n", pcie->name);
649 goto err;
650 }
651
Stefan Roese3179ec62019-01-25 11:52:43 +0100652 /* Parse PCIe controller register base from DT */
Pali Rohár3f6890d2021-12-21 12:20:16 +0100653 addr = ofnode_get_property(node, "assigned-addresses", &len);
Pali Rohár807292f2021-12-21 12:20:14 +0100654 if (!addr) {
655 printf("%s: property \"assigned-addresses\" not found\n", pcie->name);
656 ret = -FDT_ERR_NOTFOUND;
Stefan Roese3179ec62019-01-25 11:52:43 +0100657 goto err;
Pali Rohár807292f2021-12-21 12:20:14 +0100658 }
659
Pali Rohár3f6890d2021-12-21 12:20:16 +0100660 pcie->base = (void *)(u32)ofnode_translate_address(node, addr);
Pali Rohárbb26c4a2021-12-21 12:20:15 +0100661 pcie->intregs = (u32)pcie->base - fdt32_to_cpu(addr[2]);
Anton Schubert98530e92015-08-11 11:54:01 +0200662
Stefan Roese3179ec62019-01-25 11:52:43 +0100663 return 0;
Anton Schubert98530e92015-08-11 11:54:01 +0200664
Stefan Roese3179ec62019-01-25 11:52:43 +0100665err:
666 return ret;
667}
Anton Schubert98530e92015-08-11 11:54:01 +0200668
Stefan Roese3179ec62019-01-25 11:52:43 +0100669static const struct dm_pci_ops mvebu_pcie_ops = {
670 .read_config = mvebu_pcie_read_config,
671 .write_config = mvebu_pcie_write_config,
672};
Phil Sutter68010aa2015-12-25 14:41:20 +0100673
Stefan Roese3179ec62019-01-25 11:52:43 +0100674static struct driver pcie_mvebu_drv = {
675 .name = "pcie_mvebu",
676 .id = UCLASS_PCI,
677 .ops = &mvebu_pcie_ops,
678 .probe = mvebu_pcie_probe,
Simon Glass71fa5b42020-12-03 16:55:18 -0700679 .plat_auto = sizeof(struct mvebu_pcie),
Stefan Roese3179ec62019-01-25 11:52:43 +0100680};
681
682/*
683 * Use a MISC device to bind the n instances (child nodes) of the
684 * PCIe base controller in UCLASS_PCI.
685 */
686static int mvebu_pcie_bind(struct udevice *parent)
687{
Pali Rohár3f6890d2021-12-21 12:20:16 +0100688 struct mvebu_pcie **ports_pcie;
Stefan Roese3179ec62019-01-25 11:52:43 +0100689 struct mvebu_pcie *pcie;
690 struct uclass_driver *drv;
691 struct udevice *dev;
Pali Rohárca69af42021-12-21 12:20:13 +0100692 struct resource mem;
693 struct resource io;
Pali Rohár3f6890d2021-12-21 12:20:16 +0100694 int ports_count, i;
695 ofnode *ports_nodes;
Stefan Roese3179ec62019-01-25 11:52:43 +0100696 ofnode subnode;
697
Pali Rohárac2ee552021-10-22 16:22:15 +0200698 /* Lookup pci driver */
Stefan Roese3179ec62019-01-25 11:52:43 +0100699 drv = lists_uclass_lookup(UCLASS_PCI);
700 if (!drv) {
701 puts("Cannot find PCI driver\n");
702 return -ENOENT;
703 }
Pali Rohár3f6890d2021-12-21 12:20:16 +0100704
705 ports_count = ofnode_get_child_count(dev_ofnode(parent));
706 ports_pcie = calloc(ports_count, sizeof(*ports_pcie));
707 ports_nodes = calloc(ports_count, sizeof(*ports_nodes));
708 if (!ports_pcie || !ports_nodes) {
709 free(ports_pcie);
710 free(ports_nodes);
711 return -ENOMEM;
712 }
713 ports_count = 0;
Stefan Roese3179ec62019-01-25 11:52:43 +0100714
Pali Roháred9bcb92022-01-13 14:28:04 +0100715#ifdef CONFIG_ARCH_KIRKWOOD
716 mem.start = KW_DEFADR_PCI_MEM;
717 mem.end = KW_DEFADR_PCI_MEM + KW_DEFADR_PCI_MEM_SIZE - 1;
718 io.start = KW_DEFADR_PCI_IO;
719 io.end = KW_DEFADR_PCI_IO + KW_DEFADR_PCI_IO_SIZE - 1;
720#else
Pali Rohárca69af42021-12-21 12:20:13 +0100721 mem.start = MBUS_PCI_MEM_BASE;
722 mem.end = MBUS_PCI_MEM_BASE + MBUS_PCI_MEM_SIZE - 1;
723 io.start = MBUS_PCI_IO_BASE;
724 io.end = MBUS_PCI_IO_BASE + MBUS_PCI_IO_SIZE - 1;
Pali Roháred9bcb92022-01-13 14:28:04 +0100725#endif
Pali Rohárca69af42021-12-21 12:20:13 +0100726
Pali Rohár3f6890d2021-12-21 12:20:16 +0100727 /* First phase: Fill mvebu_pcie struct for each port */
Stefan Roese3179ec62019-01-25 11:52:43 +0100728 ofnode_for_each_subnode(subnode, dev_ofnode(parent)) {
729 if (!ofnode_is_available(subnode))
730 continue;
731
732 pcie = calloc(1, sizeof(*pcie));
733 if (!pcie)
Pali Rohár3f6890d2021-12-21 12:20:16 +0100734 continue;
735
736 if (mvebu_pcie_port_parse_dt(subnode, dev_ofnode(parent), pcie) < 0) {
737 free(pcie);
738 continue;
739 }
Stefan Roese3179ec62019-01-25 11:52:43 +0100740
Pali Rohárca69af42021-12-21 12:20:13 +0100741 /*
742 * MVEBU PCIe controller needs MEMORY and I/O BARs to be mapped
743 * into SoCs address space. Each controller will map 128M of MEM
744 * and 64K of I/O space when registered.
745 */
746
747 if (resource_size(&mem) >= SZ_128M) {
748 pcie->mem.start = mem.start;
749 pcie->mem.end = mem.start + SZ_128M - 1;
750 mem.start += SZ_128M;
751 } else {
Pali Rohár3f6890d2021-12-21 12:20:16 +0100752 printf("%s: unable to assign mbus window for mem\n", pcie->name);
Pali Rohárca69af42021-12-21 12:20:13 +0100753 pcie->mem.start = 0;
754 pcie->mem.end = -1;
755 }
756
757 if (resource_size(&io) >= SZ_64K) {
758 pcie->io.start = io.start;
759 pcie->io.end = io.start + SZ_64K - 1;
760 io.start += SZ_64K;
761 } else {
Pali Rohár3f6890d2021-12-21 12:20:16 +0100762 printf("%s: unable to assign mbus window for io\n", pcie->name);
Pali Rohárca69af42021-12-21 12:20:13 +0100763 pcie->io.start = 0;
764 pcie->io.end = -1;
765 }
766
Pali Rohár3f6890d2021-12-21 12:20:16 +0100767 ports_pcie[ports_count] = pcie;
768 ports_nodes[ports_count] = subnode;
769 ports_count++;
770 }
771
772 /* Second phase: Setup all PCIe links (do not enable them yet) */
773 for (i = 0; i < ports_count; i++)
774 mvebu_pcie_setup_link(ports_pcie[i]);
775
776 /* Third phase: Enable all PCIe links and create for each UCLASS_PCI device */
777 for (i = 0; i < ports_count; i++) {
778 pcie = ports_pcie[i];
779 subnode = ports_nodes[i];
780
781 /*
782 * PCIe link can be enabled only after all PCIe links were
783 * properly configured. This is because more PCIe links shares
784 * one enable bit and some PCIe links cannot be enabled
785 * individually.
786 */
787 if (mvebu_pcie_enable_link(pcie, subnode) < 0) {
788 free(pcie);
789 continue;
790 }
791
Stefan Roese3179ec62019-01-25 11:52:43 +0100792 /* Create child device UCLASS_PCI and bind it */
Simon Glass884870f2020-11-28 17:50:01 -0700793 device_bind(parent, &pcie_mvebu_drv, pcie->name, pcie, subnode,
794 &dev);
Anton Schubert98530e92015-08-11 11:54:01 +0200795 }
Stefan Roese3179ec62019-01-25 11:52:43 +0100796
Pali Rohár3f6890d2021-12-21 12:20:16 +0100797 free(ports_pcie);
798 free(ports_nodes);
799
Stefan Roese3179ec62019-01-25 11:52:43 +0100800 return 0;
Anton Schubert98530e92015-08-11 11:54:01 +0200801}
Stefan Roese3179ec62019-01-25 11:52:43 +0100802
803static const struct udevice_id mvebu_pcie_ids[] = {
804 { .compatible = "marvell,armada-xp-pcie" },
805 { .compatible = "marvell,armada-370-pcie" },
Pali Roháred9bcb92022-01-13 14:28:04 +0100806 { .compatible = "marvell,kirkwood-pcie" },
Stefan Roese3179ec62019-01-25 11:52:43 +0100807 { }
808};
809
810U_BOOT_DRIVER(pcie_mvebu_base) = {
811 .name = "pcie_mvebu_base",
812 .id = UCLASS_MISC,
813 .of_match = mvebu_pcie_ids,
814 .bind = mvebu_pcie_bind,
815};