| wdenk | 5f49575 | 2004-02-26 23:46:20 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2000 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| 5 | * (C) Copyright 2002 |
| 6 | * Torsten Demke, FORCE Computers GmbH. torsten.demke@fci.com |
| 7 | * |
| Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 8 | * SPDX-License-Identifier: GPL-2.0+ |
| wdenk | 5f49575 | 2004-02-26 23:46:20 +0000 | [diff] [blame] | 9 | */ |
| 10 | #ifndef _PIIX4_PCI_H |
| 11 | #define _PIIX4_PCI_H |
| 12 | |
| 13 | #include <common.h> |
| 14 | #include <mpc824x.h> |
| 15 | #include <asm/processor.h> |
| 16 | #include <asm/io.h> |
| 17 | #include <pci.h> |
| 18 | |
| 19 | #define PIIX4_VENDOR_ID 0x8086 |
| 20 | #define PIIX4_ISA_DEV_ID 0x7110 |
| 21 | #define PIIX4_IDE_DEV_ID 0x7111 |
| 22 | |
| 23 | /* Function 0 ISA Bridge */ |
| 24 | #define PCI_CFG_PIIX4_IORT 0x4C /* 8 bit ISA Recovery Timer Reg (default 0x4D) */ |
| 25 | #define PCI_CFG_PIIX4_XBCS 0x4E /* 16 bit XBus Chip select reg (default 0x0003) */ |
| 26 | #define PCI_CFG_PIIX4_PIRQC 0x60 /* PCI IRQ Route Register 4 x 8bit (default )*/ |
| 27 | #define PCI_CFG_PIIX4_SERIRQ 0x64 |
| 28 | #define PCI_CFG_PIIX4_TOM 0x69 |
| 29 | #define PCI_CFG_PIIX4_MSTAT 0x6A |
| 30 | #define PCI_CFG_PIIX4_MBDMA 0x76 |
| 31 | #define PCI_CFG_PIIX4_APICBS 0x80 |
| 32 | #define PCI_CFG_PIIX4_DLC 0x82 |
| 33 | #define PCI_CFG_PIIX4_PDMACFG 0x90 |
| 34 | #define PCI_CFG_PIIX4_DDMABS 0x92 |
| 35 | #define PCI_CFG_PIIX4_GENCFG 0xB0 |
| 36 | #define PCI_CFG_PIIX4_RTCCFG 0xCB |
| 37 | |
| 38 | /* IO Addresses */ |
| 39 | #define PIIX4_ISA_DMA1_CH0BA 0x00 |
| 40 | #define PIIX4_ISA_DMA1_CH0CA 0x01 |
| 41 | #define PIIX4_ISA_DMA1_CH1BA 0x02 |
| 42 | #define PIIX4_ISA_DMA1_CH1CA 0x03 |
| 43 | #define PIIX4_ISA_DMA1_CH2BA 0x04 |
| 44 | #define PIIX4_ISA_DMA1_CH2CA 0x05 |
| 45 | #define PIIX4_ISA_DMA1_CH3BA 0x06 |
| 46 | #define PIIX4_ISA_DMA1_CH3CA 0x07 |
| 47 | #define PIIX4_ISA_DMA1_CMDST 0x08 |
| 48 | #define PIIX4_ISA_DMA1_REQ 0x09 |
| 49 | #define PIIX4_ISA_DMA1_WSBM 0x0A |
| 50 | #define PIIX4_ISA_DMA1_CH_MOD 0x0B |
| 51 | #define PIIX4_ISA_DMA1_CLR_PT 0x0C |
| 52 | #define PIIX4_ISA_DMA1_M_CLR 0x0D |
| 53 | #define PIIX4_ISA_DMA1_CLR_M 0x0E |
| 54 | #define PIIX4_ISA_DMA1_RWAMB 0x0F |
| 55 | |
| 56 | #define PIIX4_ISA_DMA2_CH0BA 0xC0 |
| 57 | #define PIIX4_ISA_DMA2_CH0CA 0xC1 |
| 58 | #define PIIX4_ISA_DMA2_CH1BA 0xC2 |
| 59 | #define PIIX4_ISA_DMA2_CH1CA 0xC3 |
| 60 | #define PIIX4_ISA_DMA2_CH2BA 0xC4 |
| 61 | #define PIIX4_ISA_DMA2_CH2CA 0xC5 |
| 62 | #define PIIX4_ISA_DMA2_CH3BA 0xC6 |
| 63 | #define PIIX4_ISA_DMA2_CH3CA 0xC7 |
| 64 | #define PIIX4_ISA_DMA2_CMDST 0xD0 |
| 65 | #define PIIX4_ISA_DMA2_REQ 0xD2 |
| 66 | #define PIIX4_ISA_DMA2_WSBM 0xD4 |
| 67 | #define PIIX4_ISA_DMA2_CH_MOD 0xD6 |
| 68 | #define PIIX4_ISA_DMA2_CLR_PT 0xD8 |
| 69 | #define PIIX4_ISA_DMA2_M_CLR 0xDA |
| 70 | #define PIIX4_ISA_DMA2_CLR_M 0xDC |
| 71 | #define PIIX4_ISA_DMA2_RWAMB 0xDE |
| 72 | |
| 73 | #define PIIX4_ISA_INT1_ICW1 0x20 |
| 74 | #define PIIX4_ISA_INT1_OCW2 0x20 |
| 75 | #define PIIX4_ISA_INT1_OCW3 0x20 |
| 76 | #define PIIX4_ISA_INT1_ICW2 0x21 |
| 77 | #define PIIX4_ISA_INT1_ICW3 0x21 |
| 78 | #define PIIX4_ISA_INT1_ICW4 0x21 |
| 79 | #define PIIX4_ISA_INT1_OCW1 0x21 |
| 80 | |
| 81 | #define PIIX4_ISA_INT1_ELCR 0x4D0 |
| 82 | |
| 83 | #define PIIX4_ISA_INT2_ICW1 0xA0 |
| 84 | #define PIIX4_ISA_INT2_OCW2 0xA0 |
| 85 | #define PIIX4_ISA_INT2_OCW3 0xA0 |
| 86 | #define PIIX4_ISA_INT2_ICW2 0xA1 |
| 87 | #define PIIX4_ISA_INT2_ICW3 0xA1 |
| 88 | #define PIIX4_ISA_INT2_ICW4 0xA1 |
| 89 | #define PIIX4_ISA_INT2_OCW1 0xA1 |
| 90 | #define PIIX4_ISA_INT2_IMR 0xA1 /* read only */ |
| 91 | |
| 92 | #define PIIX4_ISA_INT2_ELCR 0x4D1 |
| 93 | |
| 94 | #define PIIX4_ISA_TMR0_CNT_ST 0x40 |
| 95 | #define PIIX4_ISA_TMR1_CNT_ST 0x41 |
| 96 | #define PIIX4_ISA_TMR2_CNT_ST 0x42 |
| 97 | #define PIIX4_ISA_TMR_TCW 0x43 |
| 98 | |
| 99 | #define PIIX4_ISA_RST_XBUS 0x60 |
| 100 | |
| 101 | #define PIIX4_ISA_NMI_CNT_ST 0x61 |
| 102 | #define PIIX4_ISA_NMI_ENABLE 0x70 |
| 103 | |
| 104 | #define PIIX4_ISA_RTC_INDEX 0x70 |
| 105 | #define PIIX4_ISA_RTC_DATA 0x71 |
| 106 | #define PIIX4_ISA_RTCEXT_IND 0x70 |
| 107 | #define PIIX4_ISA_RTCEXT_DATA 0x71 |
| 108 | |
| 109 | #define PIIX4_ISA_DMA1_CH2LPG 0x81 |
| 110 | #define PIIX4_ISA_DMA1_CH3LPG 0x82 |
| 111 | #define PIIX4_ISA_DMA1_CH1LPG 0x83 |
| 112 | #define PIIX4_ISA_DMA1_CH0LPG 0x87 |
| 113 | #define PIIX4_ISA_DMA2_CH2LPG 0x89 |
| 114 | #define PIIX4_ISA_DMA2_CH3LPG 0x8A |
| 115 | #define PIIX4_ISA_DMA2_CH1LPG 0x8B |
| 116 | #define PIIX4_ISA_DMA2_LPGRFR 0x8F |
| 117 | |
| 118 | #define PIIX4_ISA_PORT_92 0x92 |
| 119 | |
| 120 | #define PIIX4_ISA_APM_CONTRL 0xB2 |
| 121 | #define PIIX4_ISA_APM_STATUS 0xB3 |
| 122 | |
| 123 | #define PIIX4_ISA_COCPU_ERROR 0xF0 |
| 124 | |
| 125 | /* Function 1 IDE Controller */ |
| 126 | #define PCI_CFG_PIIX4_BMIBA 0x20 |
| 127 | #define PCI_CFG_PIIX4_IDETIM 0x40 |
| 128 | #define PCI_CFG_PIIX4_SIDETIM 0x44 |
| 129 | #define PCI_CFG_PIIX4_UDMACTL 0x48 |
| 130 | #define PCI_CFG_PIIX4_UDMATIM 0x4A |
| 131 | |
| 132 | /* Function 2 USB Controller */ |
| 133 | #define PCI_CFG_PIIX4_SBRNUM 0x60 |
| 134 | #define PCI_CFG_PIIX4_LEGSUP 0xC0 |
| 135 | |
| 136 | /* Function 3 Power Management */ |
| 137 | #define PCI_CFG_PIIX4_PMAB 0x40 |
| 138 | #define PCI_CFG_PIIX4_CNTA 0x44 |
| 139 | #define PCI_CFG_PIIX4_CNTB 0x48 |
| 140 | #define PCI_CFG_PIIX4_GPICTL 0x4C |
| 141 | #define PCI_CFG_PIIX4_DEVRESD 0x50 |
| 142 | #define PCI_CFG_PIIX4_DEVACTA 0x54 |
| 143 | #define PCI_CFG_PIIX4_DEVACTB 0x58 |
| 144 | #define PCI_CFG_PIIX4_DEVRESA 0x5C |
| 145 | #define PCI_CFG_PIIX4_DEVRESB 0x60 |
| 146 | #define PCI_CFG_PIIX4_DEVRESC 0x64 |
| 147 | #define PCI_CFG_PIIX4_DEVRESE 0x68 |
| 148 | #define PCI_CFG_PIIX4_DEVRESF 0x6C |
| 149 | #define PCI_CFG_PIIX4_DEVRESG 0x70 |
| 150 | #define PCI_CFG_PIIX4_DEVRESH 0x74 |
| 151 | #define PCI_CFG_PIIX4_DEVRESI 0x78 |
| 152 | #define PCI_CFG_PIIX4_PMMISC 0x80 |
| 153 | #define PCI_CFG_PIIX4_SMBBA 0x90 |
| 154 | |
| 155 | |
| 156 | #endif /* _PIIX4_PCI_H */ |