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git01.mediatek.com / filogic / uboot / 084d88f3889a6dd8de0506a9ad66db34325486f7 / . / board / cssi / cmpc885 / sdram.c
blob: 828784bd368e8b8d035bd321eff6f2df712cd685 [file] [log] [blame]
Christophe Leroy1fc46f52022-10-14 12:54:50 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2020 CS Group
4 * Charles Frey <charles.frey@c-s.fr>
5 */
6
Tom Rini10e6a372023-12-14 13:16:52 -0500[diff] [blame]7#include <config.h>
Christophe Leroy1fc46f52022-10-14 12:54:50 +0200[diff] [blame]8#include <linux/sizes.h>
9#include <linux/delay.h>
10#include <init.h>
11#include <asm/io.h>
12#include <mpc8xx.h>
13#include <watchdog.h>
Christophe Leroyf4ecd0f2023-11-06 19:12:05 +0100[diff] [blame]14#include <asm/ppc.h>
15#include <asm/immap_8xx.h>
Christophe Leroy1fc46f52022-10-14 12:54:50 +0200[diff] [blame]16
17DECLARE_GLOBAL_DATA_PTR;
18
19#define ADDR_CPLD_R_TYPE ((unsigned char __iomem *)CONFIG_CPLD_BASE + 3)
20
21#define _NOT_USED_ 0xFFFFEC04
22
23static const uint sdram_table[] = {
24 /* DRAM - single read. (offset 0 in upm RAM) */
25 0x0F0CEC04, 0x0FFFEC04, 0x00AF2C04, 0x0FFFEC00,
26 0x0FFCE004, 0xFFFFEC05, _NOT_USED_, _NOT_USED_,
27
28 /* DRAM - burst read. (offset 8 in upm RAM) */
29 0x0F0CEC04, 0x0FFFEC04, 0x00AF2C04, 0x00FFEC00,
30 0x00FFEC00, 0x00FFEC00, 0x0FFCE000, 0x1FFFEC05,
31
32 /* DRAM - Precharge all banks. (offset 16 in upm RAM) */
33 _NOT_USED_, 0x0FFCE004, 0x1FFFEC05, _NOT_USED_,
34
35 /* DRAM - NOP. (offset 20 in upm RAM) */
36 0x1FFFEC05, _NOT_USED_, _NOT_USED_, _NOT_USED_,
37
38 /* DRAM - single write. (offset 24 in upm RAM) */
39 0x0F0CEC04, 0x0FFFEC00, 0x00AF2004, 0x0FFFEC04,
40 0x0FFCE004, 0x0FFFEC04, 0xFFFFEC05, _NOT_USED_,
41
42 /* DRAM - burst write. (offset 32 in upm RAM) */
43 0x0F0CEC04, 0x0FFFEC00, 0x00AF2000, 0x00FFEC00,
44 0x00FFEC00, 0x00FFEC04, 0x0FFFEC04, 0x0FFCE004,
45 0x1FFFEC05, _NOT_USED_, _NOT_USED_, _NOT_USED_,
46 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
47
48 /* refresh (offset 48 in upm RAM) */
49 0x0FFDE404, 0x0FFEAC04, 0x0FFD6C84, 0x0FFFEC04,
50 0x0FFFEC04, 0x0FFFEC04, 0x0FFFEC04, 0x1FFFEC85,
51
52 /* init (offset 56 in upm RAM) */
53 0x0FEEA874, 0x0FBD6474, 0x1FFFEC45, _NOT_USED_,
54
55 /* exception. (offset 60 in upm RAM) */
56 0x0FFCE004, 0xFFFFEC05, _NOT_USED_, _NOT_USED_
57};
58
59/* SDRAM initialization */
60int dram_init(void)
61{
62 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
63 memctl8xx_t __iomem *memctl = &immap->im_memctl;
64 u32 max_size, mamr;
65 u8 val;
66
67 printf("UPMA init for SDRAM (CAS latency 2), ");
68 printf("init address 0x%08x, size ", (int)dram_init);
69
70 /* Verify the SDRAM size of the board */
71 val = (in_8(ADDR_CPLD_R_TYPE) & 0x30) >> 4;
72
73 if (val == 0x03 || val == 0x00) {
74 max_size = 64 * SZ_1M; /* 64 Mo of SDRAM */
75 mamr = 0x20104000;
76 } else {
77 max_size = 128 * SZ_1M; /* 128 Mo of SDRAM */
78 mamr = 0x20206000;
79 }
80
81 /* Configure CS1 */
82 out_be32(&memctl->memc_or1,
83 ~(max_size - 1) | OR_CSNT_SAM | OR_ACS_DIV2);
84 out_be32(&memctl->memc_br1, CFG_SYS_SDRAM_BASE | BR_MS_UPMA | BR_V);
85
86 /* Configure UPMA for CS1 */
87 upmconfig(UPMA, (uint *)sdram_table, ARRAY_SIZE(sdram_table));
88
89 out_be16(&memctl->memc_mptpr, MPTPR_PTP_DIV32);
90 /* disable refresh */
91 out_be32(&memctl->memc_mamr, mamr);
92 udelay(100);
93
94 /* NOP to maintain DQM high */
95 out_be32(&memctl->memc_mcr, 0x80002114);
96 udelay(200);
97
98 out_be32(&memctl->memc_mcr, 0x80002111); /* PRECHARGE cmd */
99 out_be32(&memctl->memc_mcr, 0x80002830); /* AUTO REFRESH cmd */
100 out_be32(&memctl->memc_mar, 0x00000088);
101 out_be32(&memctl->memc_mcr, 0x80002138);
102
103 /* Enable refresh */
104 setbits_be32(&memctl->memc_mamr, MAMR_PTAE);
105
106 gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, max_size);
107
108 return 0;
109}