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Marcel Ziswiler315deb32023-08-04 12:08:08 +02001// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2023 Toradex
4 */
5
6#include "k3-am625-verdin-wifi-dev-binman.dtsi"
7
8/ {
9 aliases {
10 eeprom0 = &eeprom_module;
11 eeprom1 = &eeprom_carrier_board;
12 eeprom2 = &eeprom_display_adapter;
13 };
14
15 chosen {
16 tick-timer = &main_timer0;
17 };
18
19 memory@80000000 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +020020 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +020021 };
Emanuele Ghidoli26b5cba2024-02-23 10:11:41 +010022
23 sysinfo {
24 compatible = "toradex,sysinfo";
25 };
Marcel Ziswiler315deb32023-08-04 12:08:08 +020026};
27
Nishanth Menon947dc7d2023-11-14 21:28:55 -060028&main_timer0 {
29 clock-frequency = <25000000>;
Marcel Ziswiler315deb32023-08-04 12:08:08 +020030};
31
Roger Quadros74f59242023-10-28 20:36:02 +030032&main_bcdma {
33 reg = <0x00 0x485c0100 0x00 0x100>,
34 <0x00 0x4c000000 0x00 0x20000>,
35 <0x00 0x4a820000 0x00 0x20000>,
36 <0x00 0x4aa40000 0x00 0x20000>,
37 <0x00 0x4bc00000 0x00 0x100000>,
38 <0x00 0x48600000 0x00 0x8000>,
39 <0x00 0x484a4000 0x00 0x2000>,
40 <0x00 0x484c2000 0x00 0x2000>;
41 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt",
42 "ringrt" , "cfg", "tchan", "rchan";
Roger Quadros88a6b0a2023-11-14 22:28:56 +020043 bootph-all;
Roger Quadros74f59242023-10-28 20:36:02 +030044};
45
46&main_pktdma {
47 reg = <0x00 0x485c0000 0x00 0x100>,
48 <0x00 0x4a800000 0x00 0x20000>,
49 <0x00 0x4aa00000 0x00 0x20000>,
50 <0x00 0x4b800000 0x00 0x200000>,
51 <0x00 0x485e0000 0x00 0x10000>,
52 <0x00 0x484a0000 0x00 0x2000>,
53 <0x00 0x484c0000 0x00 0x2000>,
54 <0x00 0x48430000 0x00 0x1000>;
55 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
56 "cfg", "tchan", "rchan", "rflow";
57 bootph-all;
58};
59
Marcel Ziswiler315deb32023-08-04 12:08:08 +020060&cpsw3g {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +020061 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +020062};
63
64&cpsw3g_phy0 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +020065 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +020066};
67
68&cpsw3g_phy1 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +020069 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +020070};
71
72&cpsw_port1 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +020073 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +020074};
75
76&cpsw_port2 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +020077 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +020078};
79
80/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */
81&cpsw3g_mdio {
82 /delete-property/ assigned-clocks;
83 /delete-property/ assigned-clock-parents;
84 /delete-property/ assigned-clock-rates;
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +020085 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +020086};
87
Marcel Ziswiler315deb32023-08-04 12:08:08 +020088&fss {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +020089 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +020090};
91
Marcel Ziswiler315deb32023-08-04 12:08:08 +020092&main_gpio0 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +020093 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +020094};
95
96/* On-module I2C - PMIC_I2C */
97&main_i2c0 {
98 eeprom_module: eeprom@50 {
99 compatible = "i2c-eeprom";
100 pagesize = <16>;
101 reg = <0x50>;
102 };
103};
104
105/* Verdin I2C_1 */
106&main_i2c1 {
107 /* EEPROM on display adapter (MIPI DSI Display Adapter) */
108 eeprom_display_adapter: eeprom@50 {
109 compatible = "i2c-eeprom";
110 reg = <0x50>;
111 pagesize = <16>;
112 };
113
114 /* EEPROM on carrier board */
115 eeprom_carrier_board: eeprom@57 {
116 compatible = "i2c-eeprom";
117 reg = <0x57>;
118 pagesize = <16>;
119 };
120};
121
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200122/* Verdin UART_3, used as the Linux console */
123&main_uart0 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200124 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200125};
126
127/* Verdin UART_1 */
128&main_uart1 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200129 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200130};
131
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200132&pinctrl_ctrl_sleep_moci {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200133 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200134};
135
136&pinctrl_i2c0 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200137 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200138};
139
140&pinctrl_i2c1 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200141 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200142};
143
144&pinctrl_sdhci0 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200145 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200146};
147
148&pinctrl_uart0 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200149 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200150};
151
152&pinctrl_uart1 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200153 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200154};
155
156&pinctrl_wkup_uart0 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200157 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200158};
159
160&sdhci0 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200161 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200162};
163
164&sdhci2 {
165 status = "disabled";
166};
167
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200168&verdin_ctrl_sleep_moci {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200169 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200170};
171
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200172/* Verdin UART_2 */
173&wkup_uart0 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200174 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200175};