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git01.mediatek.com / filogic / uboot / 08441575905a69d34a9bebc1d2672aa89a3c3f32 / . / arch / mips / dts / mt7628a.dtsi
blob: e9241a0737f5e08f4927ae8be3948c44634cb4c1 [file] [log] [blame]
Stefan Roese65da15e2018-09-05 15:12:35 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2
3/ {
4 #address-cells = <1>;
5 #size-cells = <1>;
6 compatible = "ralink,mt7628a-soc";
7
8 cpus {
9 #address-cells = <1>;
10 #size-cells = <0>;
11
12 cpu@0 {
13 compatible = "mti,mips24KEc";
14 device_type = "cpu";
15 reg = <0>;
16 };
17 };
18
19 resetc: reset-controller {
20 compatible = "ralink,rt2880-reset";
21 #reset-cells = <1>;
22 };
23
24 cpuintc: interrupt-controller {
25 #address-cells = <0>;
26 #interrupt-cells = <1>;
27 interrupt-controller;
28 compatible = "mti,cpu-interrupt-controller";
29 };
30
31 palmbus@10000000 {
32 compatible = "palmbus", "simple-bus";
33 reg = <0x10000000 0x200000>;
34 ranges = <0x0 0x10000000 0x1FFFFF>;
35
36 #address-cells = <1>;
37 #size-cells = <1>;
38
39 sysc: system-controller@0 {
40 compatible = "ralink,mt7620a-sysc", "syscon";
41 reg = <0x0 0x100>;
42 };
43
Stefan Roese845e0fd2018-08-16 15:27:32 +0200[diff] [blame]44 syscon-reboot {
45 compatible = "syscon-reboot";
46 regmap = <&sysc>;
47 offset = <0x34>;
48 mask = <0x1>;
49 };
50
Stefan Roese787d22b2018-10-09 08:59:08 +0200[diff] [blame]51 watchdog: watchdog@100 {
52 compatible = "ralink,mt7628a-wdt", "mediatek,mt7621-wdt";
53 reg = <0x100 0x30>;
54
55 resets = <&resetc 8>;
56 reset-names = "wdt";
57
58 interrupt-parent = <&intc>;
59 interrupts = <24>;
60 };
61
Stefan Roese65da15e2018-09-05 15:12:35 +0200[diff] [blame]62 intc: interrupt-controller@200 {
63 compatible = "ralink,rt2880-intc";
64 reg = <0x200 0x100>;
65
66 interrupt-controller;
67 #interrupt-cells = <1>;
68
69 resets = <&resetc 9>;
70 reset-names = "intc";
71
72 interrupt-parent = <&cpuintc>;
73 interrupts = <2>;
74
75 ralink,intc-registers = <0x9c 0xa0
76 0x6c 0xa4
77 0x80 0x78>;
78 };
79
80 memory-controller@300 {
81 compatible = "ralink,mt7620a-memc";
82 reg = <0x300 0x100>;
83 };
84
Stefan Roese4e453bd2018-10-09 08:59:07 +0200[diff] [blame]85 gpio@600 {
86 #address-cells = <1>;
87 #size-cells = <0>;
88
89 compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
90 reg = <0x600 0x100>;
91
92 interrupt-parent = <&intc>;
93 interrupts = <6>;
94
95 gpio0: bank@0 {
96 reg = <0>;
97 compatible = "mtk,mt7621-gpio-bank";
98 gpio-controller;
99 #gpio-cells = <2>;
100 };
101
102 gpio1: bank@1 {
103 reg = <1>;
104 compatible = "mtk,mt7621-gpio-bank";
105 gpio-controller;
106 #gpio-cells = <2>;
107 };
108
109 gpio2: bank@2 {
110 reg = <2>;
111 compatible = "mtk,mt7621-gpio-bank";
112 gpio-controller;
113 #gpio-cells = <2>;
114 };
115 };
116
Stefan Roese65da15e2018-09-05 15:12:35 +0200[diff] [blame]117 spi0: spi@b00 {
118 compatible = "ralink,mt7621-spi";
119 reg = <0xb00 0x40>;
120 #address-cells = <1>;
121 #size-cells = <0>;
Stefan Roese9a4e1552018-08-16 15:27:33 +0200[diff] [blame]122
123 clock-frequency = <200000000>;
Stefan Roese65da15e2018-09-05 15:12:35 +0200[diff] [blame]124 };
125
126 uart0: uartlite@c00 {
developer08441572019-09-25 17:45:20 +0800[diff] [blame^]127 compatible = "mediatek,hsuart", "ns16550a";
Stefan Roese65da15e2018-09-05 15:12:35 +0200[diff] [blame]128 reg = <0xc00 0x100>;
129
developera799f392019-09-25 17:45:19 +0800[diff] [blame]130 clock-frequency = <40000000>;
131
Stefan Roese65da15e2018-09-05 15:12:35 +0200[diff] [blame]132 resets = <&resetc 12>;
133 reset-names = "uart0";
134
135 interrupt-parent = <&intc>;
136 interrupts = <20>;
137
138 reg-shift = <2>;
139 };
140
141 uart1: uart1@d00 {
developer08441572019-09-25 17:45:20 +0800[diff] [blame^]142 compatible = "mediatek,hsuart", "ns16550a";
Stefan Roese65da15e2018-09-05 15:12:35 +0200[diff] [blame]143 reg = <0xd00 0x100>;
144
developera799f392019-09-25 17:45:19 +0800[diff] [blame]145 clock-frequency = <40000000>;
146
Stefan Roese65da15e2018-09-05 15:12:35 +0200[diff] [blame]147 resets = <&resetc 19>;
148 reset-names = "uart1";
149
150 interrupt-parent = <&intc>;
151 interrupts = <21>;
152
153 reg-shift = <2>;
154 };
155
156 uart2: uart2@e00 {
developer08441572019-09-25 17:45:20 +0800[diff] [blame^]157 compatible = "mediatek,hsuart", "ns16550a";
Stefan Roese65da15e2018-09-05 15:12:35 +0200[diff] [blame]158 reg = <0xe00 0x100>;
159
developera799f392019-09-25 17:45:19 +0800[diff] [blame]160 clock-frequency = <40000000>;
161
Stefan Roese65da15e2018-09-05 15:12:35 +0200[diff] [blame]162 resets = <&resetc 20>;
163 reset-names = "uart2";
164
165 interrupt-parent = <&intc>;
166 interrupts = <22>;
167
168 reg-shift = <2>;
169 };
170 };
171
Stefan Roesec35b97f2018-10-09 08:59:06 +0200[diff] [blame]172 eth@10110000 {
Stefan Roesefbf49802018-11-28 08:40:48 +0100[diff] [blame]173 compatible = "mediatek,mt7628-eth";
Stefan Roesec35b97f2018-10-09 08:59:06 +0200[diff] [blame]174 reg = <0x10100000 0x10000
175 0x10110000 0x8000>;
176
177 syscon = <&sysc>;
178 };
179
Stefan Roese65da15e2018-09-05 15:12:35 +0200[diff] [blame]180 usb_phy: usb-phy@10120000 {
181 compatible = "mediatek,mt7628-usbphy";
182 reg = <0x10120000 0x1000>;
183
184 #phy-cells = <0>;
185
186 ralink,sysctl = <&sysc>;
187 resets = <&resetc 22 &resetc 25>;
188 reset-names = "host", "device";
189 };
190
191 ehci@101c0000 {
192 compatible = "generic-ehci";
193 reg = <0x101c0000 0x1000>;
194
195 phys = <&usb_phy>;
196 phy-names = "usb";
197
198 interrupt-parent = <&intc>;
199 interrupts = <18>;
200 };
201};