blob: 3e58bf97cc417366b4bbbddf6979b89534fa11e2 [file] [log] [blame]
Svyatoslav Ryhel88fd1562023-06-30 10:29:04 +03001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * T30 Grouper MAX SPL stage configuration
4 *
5 * (C) Copyright 2010-2013
6 * NVIDIA Corporation <www.nvidia.com>
7 *
8 * (C) Copyright 2022
9 * Svyatoslav Ryhel <clamor95@gmail.com>
10 */
11
Svyatoslav Ryhel193e9482023-08-26 18:46:27 +030012#include <asm/arch/tegra.h>
Svyatoslav Ryhel88fd1562023-06-30 10:29:04 +030013#include <asm/arch-tegra/tegra_i2c.h>
14#include <linux/delay.h>
15
16#define MAX77663_I2C_ADDR (0x3C << 1)
17
18#define MAX77663_REG_SD0 0x16
19#define MAX77663_REG_SD0_DATA (0x2100 | MAX77663_REG_SD0)
20#define MAX77663_REG_SD1 0x17
21#define MAX77663_REG_SD1_DATA (0x3000 | MAX77663_REG_SD1)
22#define MAX77663_REG_LDO4 0x2B
23#define MAX77663_REG_LDO4_DATA (0xE000 | MAX77663_REG_LDO4)
24
25#define MAX77663_REG_GPIO4 0x3A
26#define MAX77663_REG_GPIO4_DATA (0x0100 | MAX77663_REG_GPIO4)
27
28void pmic_enable_cpu_vdd(void)
29{
30 /* Set VDD_CORE to 1.200V. */
31 tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_SD1_DATA);
32
33 udelay(1000);
34
35 /* Bring up VDD_CPU to 1.0125V. */
36 tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_SD0_DATA);
37 udelay(1000);
38
39 /* Bring up VDD_RTC to 1.200V. */
40 tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_LDO4_DATA);
41 udelay(10 * 1000);
42
43 /* Set 32k-out gpio state */
44 tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_GPIO4_DATA);
45}