| Svyatoslav Ryhel | 7a25c38 | 2023-06-30 10:29:03 +0300 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /dts-v1/; |
| 3 | |
| 4 | #include "tegra30-asus-transformer.dtsi" |
| 5 | |
| 6 | / { |
| 7 | model = "ASUS Transformer Pad LTE TF300TL"; |
| 8 | compatible = "asus,tf300tl", "nvidia,tegra30"; |
| Svyatoslav Ryhel | f3947d4 | 2023-11-27 19:20:21 +0200 | [diff] [blame] | 9 | |
| 10 | pinmux@70000868 { |
| 11 | state_default: pinmux { |
| 12 | lcd_pwr2_pc6 { |
| 13 | nvidia,pins = "lcd_pwr2_pc6", |
| 14 | "lcd_dc1_pd2"; |
| 15 | nvidia,function = "displaya"; |
| 16 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 17 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 18 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 19 | }; |
| 20 | |
| 21 | pbb3 { |
| 22 | nvidia,pins = "pbb3"; |
| 23 | nvidia,function = "vgp3"; |
| 24 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 25 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 26 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 27 | }; |
| 28 | |
| 29 | pbb7 { |
| 30 | nvidia,pins = "pbb7"; |
| 31 | nvidia,function = "i2s4"; |
| 32 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 33 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 34 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 35 | }; |
| 36 | |
| 37 | kb_row7_pr7 { |
| 38 | nvidia,pins = "kb_row7_pr7"; |
| 39 | nvidia,function = "kbc"; |
| 40 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 41 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 42 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 43 | }; |
| 44 | |
| 45 | gmi_cs4_n_pk2 { |
| 46 | nvidia,pins = "gmi_cs4_n_pk2"; |
| 47 | nvidia,function = "gmi"; |
| 48 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 49 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 50 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 51 | }; |
| 52 | |
| 53 | /* TF300TL specific pinmux reconfiguration */ |
| 54 | |
| 55 | ulpi_data5_po6 { |
| 56 | nvidia,pins = "ulpi_data5_po6"; |
| 57 | nvidia,function = "uarta"; |
| 58 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 59 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 60 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 61 | }; |
| 62 | |
| 63 | dap3_din_pp1 { |
| 64 | nvidia,pins = "dap3_din_pp1"; |
| 65 | nvidia,function = "i2s2"; |
| 66 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 67 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 68 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 69 | }; |
| 70 | |
| 71 | crt_hsync_pv6 { |
| 72 | nvidia,pins = "crt_hsync_pv6"; |
| 73 | nvidia,function = "crt"; |
| 74 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 75 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 76 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 77 | }; |
| 78 | |
| 79 | crt_vsync_pv7 { |
| 80 | nvidia,pins = "crt_vsync_pv7"; |
| 81 | nvidia,function = "crt"; |
| 82 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 83 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 84 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 85 | }; |
| 86 | |
| 87 | pu5 { |
| 88 | nvidia,pins = "pu5"; |
| 89 | nvidia,function = "pwm2"; |
| 90 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 91 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 92 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 93 | }; |
| 94 | |
| 95 | clk3_out_pee0 { |
| 96 | nvidia,pins = "clk3_out_pee0"; |
| 97 | nvidia,function = "extperiph3"; |
| 98 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 99 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 100 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 101 | }; |
| 102 | |
| 103 | clk3_req_pee1 { |
| 104 | nvidia,pins = "clk3_req_pee1"; |
| 105 | nvidia,function = "dev3"; |
| 106 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 107 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 108 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 109 | }; |
| 110 | |
| 111 | dap1_fs_pn0 { |
| 112 | nvidia,pins = "dap1_fs_pn0", |
| 113 | "dap1_sclk_pn3"; |
| 114 | nvidia,function = "i2s0"; |
| 115 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 116 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 117 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 118 | }; |
| 119 | |
| 120 | dap1_din_pn1 { |
| 121 | nvidia,pins = "dap1_din_pn1"; |
| 122 | nvidia,function = "i2s0"; |
| 123 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 124 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 125 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 126 | }; |
| 127 | |
| 128 | dap1_dout_pn2 { |
| 129 | nvidia,pins = "dap1_dout_pn2"; |
| 130 | nvidia,function = "i2s0"; |
| 131 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 132 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 133 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 134 | }; |
| 135 | |
| 136 | clk1_req_pee2 { |
| 137 | nvidia,pins = "clk1_req_pee2"; |
| 138 | nvidia,function = "dap"; |
| 139 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 140 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 141 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 142 | }; |
| 143 | |
| 144 | spi2_mosi_px0 { |
| 145 | nvidia,pins = "spi2_mosi_px0"; |
| 146 | nvidia,function = "spi2"; |
| 147 | }; |
| 148 | |
| 149 | spi1_sck_px5 { |
| 150 | nvidia,pins = "spi1_sck_px5"; |
| 151 | nvidia,function = "spi1"; |
| 152 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 153 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 154 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 155 | }; |
| 156 | |
| 157 | spi1_miso_px7 { |
| 158 | nvidia,pins = "spi1_miso_px7"; |
| 159 | nvidia,function = "spi1"; |
| 160 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 161 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 162 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 163 | }; |
| 164 | |
| 165 | spi2_cs2_n_pw3 { |
| 166 | nvidia,pins = "spi2_cs2_n_pw3"; |
| 167 | nvidia,function = "spi2"; |
| 168 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 169 | }; |
| 170 | }; |
| 171 | }; |
| Svyatoslav Ryhel | 7a25c38 | 2023-06-30 10:29:03 +0300 | [diff] [blame] | 172 | }; |