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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Heiko Schocher44a93442015-06-29 09:10:48 +02002/*
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
6 *
7 * (C) Copyright 2010
8 * Achim Ehrlich <aehrlich@taskit.de>
9 * taskit GmbH <www.taskit.de>
10 *
11 * (C) Copyright 2012
12 * Markus Hubig <mhubig@imko.de>
13 * IMKO GmbH <www.imko.de>
14 *
15 * (C) Copyright 2014
16 * Heiko Schocher <hs@denx.de>
17 * DENX Software Engineering GmbH
18 *
19 * Configuation settings for the smartweb.
Heiko Schocher44a93442015-06-29 09:10:48 +020020 */
21
22#ifndef __CONFIG_H
23#define __CONFIG_H
24
25/*
26 * SoC must be defined first, before hardware.h is included.
27 * In this case SoC is defined in boards.cfg.
28 */
29#include <asm/hardware.h>
Heiko Schochercf5137c2015-09-08 11:52:52 +020030#include <linux/sizes.h>
Heiko Schocher44a93442015-06-29 09:10:48 +020031
32/*
33 * Warning: changing CONFIG_SYS_TEXT_BASE requires adapting the initial boot
34 * program. Since the linker has to swallow that define, we must use a pure
35 * hex number here!
36 */
Heiko Schocher44a93442015-06-29 09:10:48 +020037
38/* ARM asynchronous clock */
39#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
40#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */
41
42/* misc settings */
Heiko Schocher44a93442015-06-29 09:10:48 +020043
Matthias Michel0ae5e922016-01-27 15:56:07 +010044/* We set the max number of command args high to avoid HUSH bugs. */
45#define CONFIG_SYS_MAXARGS 32
46
Heiko Schocher44a93442015-06-29 09:10:48 +020047/* setting board specific options */
Matthias Michel0ae5e922016-01-27 15:56:07 +010048#define CONFIG_SYS_AUTOLOAD "yes"
49#define CONFIG_RESET_TO_RETRY
Heiko Schocher44a93442015-06-29 09:10:48 +020050
51/* The LED PINs */
52#define CONFIG_RED_LED AT91_PIN_PA9
53#define CONFIG_GREEN_LED AT91_PIN_PA6
54
55/*
56 * SDRAM: 1 bank, 64 MB, base address 0x20000000
57 * Already initialized before u-boot gets started.
58 */
Heiko Schocher44a93442015-06-29 09:10:48 +020059#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
Heiko Schochercf5137c2015-09-08 11:52:52 +020060#define CONFIG_SYS_SDRAM_SIZE (64 * SZ_1M)
Heiko Schocher44a93442015-06-29 09:10:48 +020061
62/*
63 * Perform a SDRAM Memtest from the start of SDRAM
64 * till the beginning of the U-Boot position in RAM.
65 */
Heiko Schocher44a93442015-06-29 09:10:48 +020066
Heiko Schocher44a93442015-06-29 09:10:48 +020067/* NAND flash settings */
Heiko Schocher44a93442015-06-29 09:10:48 +020068#define CONFIG_SYS_MAX_NAND_DEVICE 1
69#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
70#define CONFIG_SYS_NAND_DBW_8
71#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
72#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
73#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
74#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
75
Heiko Schocher44a93442015-06-29 09:10:48 +020076/* general purpose I/O */
77#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
Heiko Schocher44a93442015-06-29 09:10:48 +020078#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */
79
80/* serial console */
Heiko Schocher44a93442015-06-29 09:10:48 +020081#define CONFIG_USART_BASE ATMEL_BASE_DBGU
82#define CONFIG_USART_ID ATMEL_ID_SYS
Heiko Schocher44a93442015-06-29 09:10:48 +020083
84/*
85 * Ethernet configuration
86 *
87 */
88#define CONFIG_MACB
89#define CONFIG_RMII /* use reduced MII inteface */
90#define CONFIG_NET_RETRY_COUNT 20 /* # of DHCP/BOOTP retries */
91#define CONFIG_AT91_WANTS_COMMON_PHY
92
93/* BOOTP and DHCP options */
94#define CONFIG_BOOTP_BOOTFILESIZE
Tom Rini9aed2af2021-08-19 14:29:00 -040095#define NFSBOOTCOMMAND \
Heiko Schocher44a93442015-06-29 09:10:48 +020096 "setenv autoload yes; setenv autoboot yes; " \
97 "setenv bootargs ${basicargs} ${mtdparts} " \
98 "root=/dev/nfs ip=dhcp nfsroot=${serverip}:/srv/nfs/rootfs; " \
99 "dhcp"
100
Heiko Schocher44a93442015-06-29 09:10:48 +0200101#if !defined(CONFIG_SPL_BUILD)
102/* USB configuration */
103#define CONFIG_USB_ATMEL
104#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
105#define CONFIG_USB_OHCI_NEW
Heiko Schocher44a93442015-06-29 09:10:48 +0200106#define CONFIG_SYS_USB_OHCI_CPU_INIT
107#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE
108#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
109#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Heiko Schochercf5137c2015-09-08 11:52:52 +0200110
Heiko Schochercf5137c2015-09-08 11:52:52 +0200111/* USB DFU support */
Heiko Schochercf5137c2015-09-08 11:52:52 +0200112
Heiko Schochercf5137c2015-09-08 11:52:52 +0200113#define CONFIG_USB_GADGET_AT91
114
115/* DFU class support */
Heiko Schochercf5137c2015-09-08 11:52:52 +0200116#define DFU_MANIFEST_POLL_TIMEOUT 25000
Heiko Schocher44a93442015-06-29 09:10:48 +0200117#endif
118
119/* General Boot Parameter */
Heiko Schocher44a93442015-06-29 09:10:48 +0200120#define CONFIG_BOOTCOMMAND "run flashboot"
Heiko Schocher44a93442015-06-29 09:10:48 +0200121#define CONFIG_SYS_CBSIZE 512
Heiko Schocher44a93442015-06-29 09:10:48 +0200122
123/*
Heiko Schocher44a93442015-06-29 09:10:48 +0200124 * The NAND Flash partitions:
125 */
Heiko Schochercf5137c2015-09-08 11:52:52 +0200126#define CONFIG_ENV_RANGE (SZ_512K)
Heiko Schocher44a93442015-06-29 09:10:48 +0200127
128/*
129 * Predefined environment variables.
130 * Usefull to define some easy to use boot commands.
131 */
132#define CONFIG_EXTRA_ENV_SETTINGS \
133 \
134 "basicargs=console=ttyS0,115200\0" \
135 \
Tom Rini5ad8e112017-10-22 17:55:07 -0400136 "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0"
Heiko Schocher44a93442015-06-29 09:10:48 +0200137
Heiko Schocher44a93442015-06-29 09:10:48 +0200138#ifdef CONFIG_SPL_BUILD
139#define CONFIG_SYS_INIT_SP_ADDR 0x301000
140#define CONFIG_SPL_STACK_R
141#define CONFIG_SPL_STACK_R_ADDR CONFIG_SYS_TEXT_BASE
142#else
143/*
144 * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
145 * leaving the correct space for initial global data structure above that
146 * address while providing maximum stack area below.
147 */
148#define CONFIG_SYS_INIT_SP_ADDR \
149 (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
150#endif
151
Heiko Schocher44a93442015-06-29 09:10:48 +0200152/* Defines for SPL */
Heiko Schochercf5137c2015-09-08 11:52:52 +0200153#define CONFIG_SPL_MAX_SIZE (SZ_4K)
Heiko Schocher44a93442015-06-29 09:10:48 +0200154
155#define CONFIG_SPL_BSS_START_ADDR CONFIG_SYS_SDRAM_BASE
Heiko Schochercf5137c2015-09-08 11:52:52 +0200156#define CONFIG_SPL_BSS_MAX_SIZE (SZ_16K)
Heiko Schocher44a93442015-06-29 09:10:48 +0200157#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
158 CONFIG_SPL_BSS_MAX_SIZE)
159#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
Heiko Schocher44a93442015-06-29 09:10:48 +0200160
Heiko Schocher44a93442015-06-29 09:10:48 +0200161#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14)
Heiko Schocher44a93442015-06-29 09:10:48 +0200162#define CONFIG_SYS_USE_NANDFLASH 1
Heiko Schocher44a93442015-06-29 09:10:48 +0200163#define CONFIG_SPL_NAND_RAW_ONLY
164#define CONFIG_SPL_NAND_SOFTECC
165#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
Heiko Schochercf5137c2015-09-08 11:52:52 +0200166#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
Heiko Schocher44a93442015-06-29 09:10:48 +0200167#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
168#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
169#define CONFIG_SYS_NAND_5_ADDR_CYCLE
170
Heiko Schochercf5137c2015-09-08 11:52:52 +0200171#define CONFIG_SYS_NAND_SIZE (SZ_256M)
172#define CONFIG_SYS_NAND_PAGE_SIZE SZ_2K
173#define CONFIG_SYS_NAND_BLOCK_SIZE (SZ_128K)
Heiko Schocher44a93442015-06-29 09:10:48 +0200174#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
175 CONFIG_SYS_NAND_PAGE_SIZE)
176#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
177#define CONFIG_SYS_NAND_ECCSIZE 256
178#define CONFIG_SYS_NAND_ECCBYTES 3
179#define CONFIG_SYS_NAND_OOBSIZE 64
180#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
181 48, 49, 50, 51, 52, 53, 54, 55, \
182 56, 57, 58, 59, 60, 61, 62, 63, }
183
184#define CONFIG_SPL_ATMEL_SIZE
185#define CONFIG_SYS_MASTER_CLOCK (198656000/2)
186#define AT91_PLL_LOCK_TIMEOUT 1000000
187#define CONFIG_SYS_AT91_PLLA 0x2060bf09
188#define CONFIG_SYS_MCKR 0x100
189#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR)
190#define CONFIG_SYS_AT91_PLLB 0x10483f0e
191
Stefan Roese67bcbef2019-04-02 10:57:25 +0200192#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS
193#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
194
Heiko Schocher44a93442015-06-29 09:10:48 +0200195#endif /* __CONFIG_H */