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git01.mediatek.com / filogic / uboot / 07dde1e1a07a553c8ac89c313914115106be0284 / . / board / sacsng / ioconfig.h
blob: be1ce7c835826c9e3ccc226e376a2edc289f0400 [file] [log] [blame]
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]1/*
2 * I/O Port configuration table
3 *
4 * If conf is 1, then that port pin will be configured at boot time
5 * according to the five values podr/pdir/ppar/psor/pdat for that entry
6 */
7
8#ifdef SKIP
9#undef SKIP
10#endif
11
12#ifdef CONF
13#undef CONF
14#endif
15
16#ifdef DIN
17#undef DIN
18#endif
19
20#ifdef DOUT
21#undef DOUT
22#endif
23
24#ifdef GPIO
25#undef GPIO
26#endif
27
28#ifdef SPEC
29#undef SPEC
30#endif
31
32#ifdef ACTV
33#undef ACTV
34#endif
35
36#ifdef OPEN
37#undef OPEN
38#endif
39
40#define SKIP 0 /* SKIP over this port */
41#define CONF 1 /* CONFiguration the port */
42
43#define DIN 0 /* PDIRx 0: Direction IN */
44#define DOUT 1 /* PDIRx 1: Direction OUT */
45
46#define GPIO 0 /* PPARx 0: General Purpose I/O */
47#define SPEC 1 /* PPARx 1: dedicated to a peripheral function, */
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]48 /* i.e. the port has a SPECial use. */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]49
50#define ACTV 0 /* PODRx 0: ACTiVely driven as an output */
51#define OPEN 1 /* PODRx 1: OPEN-drain driver */
52
53const iop_conf_t iop_conf_tab[4][32] = {
54
55 /* Port A configuration */
56 { /* conf ppar psor pdir podr pdat */
57 /* PA31 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS8* */
58 /* PA30 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS7* */
59 /* PA29 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS6* */
60 /* PA28 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS5* */
61 /* PA27 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS4* */
62 /* PA26 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS3* */
63 /* PA25 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS2* */
64 /* PA24 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS1* */
65 /* PA23 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* ODIS_EN* */
66 /* PA22 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* STLED2_EN* */
67 /* PA21 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* STLED1_EN* */
68 /* PA20 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* PLED3_EN* */
69 /* PA19 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* PLED2_EN* */
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]70 /* PA18 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* PLED1_EN* */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]71 /* PA17 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
72 /* PA16 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* DAC_RST* */
73 /* PA15 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* CH34SDATA_PU */
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]74 /* PA14 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* CH12SDATA_PU */
75 /* PA13 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* SLRCLK_EN* */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]76 /* PA12 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_4ACDC* */
77 /* PA11 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_4TEDS* */
78 /* PA10 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_4XTDS* */
79 /* PA9 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_3ACDC* */
80 /* PA8 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_3TEDS* */
81 /* PA7 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_3XTDS* */
82 /* PA6 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_2ACDC* */
83 /* PA5 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_2TEDS* */
84 /* PA4 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_2XTDS* */
85 /* PA3 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
86 /* PA2 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_1ACDC* */
87 /* PA1 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_1TEDS* */
88 /* PA0 */ { CONF, GPIO, 0, DOUT, ACTV, 1 } /* MTRX_1XTDS* */
89 },
90
91 /* Port B configuration */
92 { /* conf ppar psor pdir podr pdat */
93 /* PB31 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TX_ER */
94 /* PB30 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RX_DV */
95 /* PB29 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* FCC2 MII_TX_EN */
96 /* PB28 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RX_ER */
97 /* PB27 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_COL */
98 /* PB26 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_CRS */
99 /* PB25 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TXD3 */
100 /* PB24 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TXD2 */
101 /* PB23 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TXD1 */
102 /* PB22 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TXD0 */
103 /* PB21 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RXD0 */
104 /* PB20 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RXD1 */
105 /* PB19 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RXD2 */
106 /* PB18 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RXD3 */
107 /* PB17 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
108 /* PB16 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
109 /* PB15 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
110 /* PB14 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1RXDC1, BSDATA_ADC12 */
111 /* PB13 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
112 /* PB12 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1RSYNCC1, LRCLK */
113 /* PB11 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1TXDD1, RSDATA_DAC12 */
114 /* PB10 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1RXDD1, BSDATA_ADC34 */
115 /* PB9 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
116 /* PB8 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1RSYNCD1, LRCLK */
117 /* PB7 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
118 /* PB6 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* XCITE_SHDN */
119 /* PB5 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* TRIGGER */
120 /* PB4 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* ARM */
121 /* PB3 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */
122 /* PB2 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */
123 /* PB1 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */
124 /* PB0 */ { SKIP, GPIO, 0, DIN, ACTV, 0 } /* pin doesn't exist */
125 },
126
127 /* Port C */
128 { /* conf ppar psor pdir podr pdat */
129 /* PC31 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
130 /* PC30 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
131 /* PC29 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK3, MCLK */
132 /* PC28 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* TOUT2* */
133#ifdef QQQ
134 /* PC28 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* TOUT2* */
135#endif
136 /* PC27 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK5, SCLK */
137 /* PC26 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
138 /* PC25 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK7, SCLK */
139 /* PC24 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
140 /* PC23 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK9, MCLK */
141 /* PC22 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
142 /* PC21 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* BRGO6 (LRCLK) */
143 /* PC20 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
144 /* PC19 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK13, MII_RXCLK */
145 /* PC18 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK14, MII_TXCLK */
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]146 /* PC17 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* BRGO8 (SCLK) */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]147 /* PC16 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
148 /* PC15 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* SMC2_TX */
149 /* PC14 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
150 /* PC13 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
151 /* PC12 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* TDM_STRB3 */
152 /* PC11 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
153 /* PC10 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* TDM_STRB4 */
154 /* PC9 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BPDIS_IN3 */
155 /* PC8 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BPDIS_IN2 */
156 /* PC7 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BPDIS_IN1 */
157 /* PC6 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
158 /* PC5 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BTST_IN2* */
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]159 /* PC4 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BTST_IN1* */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]160 /* PC3 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* MUSH_STAT */
161 /* PC2 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* OUTDRV_STAT */
162 /* PC1 */ { CONF, GPIO, 0, DOUT, OPEN, 1 }, /* PHY_MDIO */
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]163 /* PC0 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* PHY_MDC */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]164 },
165
166 /* Port D */
167 { /* conf ppar psor pdir podr pdat */
168 /* PD31 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* SCC1_RX */
169 /* PD30 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* SCC1_TX */
170 /* PD29 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
171 /* PD28 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
172 /* PD27 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
173 /* PD26 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
174 /* PD25 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
175 /* PD24 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
176 /* PD23 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
177 /* PD22 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
178 /* PD21 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
179 /* PD20 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* SPI_ADC_CS* */
180 /* PD19 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* SPI_DAC_CS* */
181#if defined(CONFIG_SOFT_SPI)
182 /* PD18 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* SPI_CLK */
183 /* PD17 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* SPI_MOSI */
184 /* PD16 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* SPI_MISO */
185#else
186 /* PD18 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* SPI_CLK */
187 /* PD17 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* SPI_MOSI */
188 /* PD16 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* SPI_MISO */
189#endif
190#if defined(CONFIG_SOFT_I2C)
191 /* PD15 */ { CONF, GPIO, 0, DOUT, OPEN, 1 }, /* I2C_SDA */
192 /* PD14 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* I2C_SCL */
193#else
194#if defined(CONFIG_HARD_I2C)
195 /* PD15 */ { CONF, SPEC, 1, DIN, OPEN, 0 }, /* I2C_SDA */
196 /* PD14 */ { CONF, SPEC, 1, DIN, OPEN, 0 }, /* I2C_SCL */
197#else /* normal I/O port pins */
198 /* PD15 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* I2C_SDA */
199 /* PD14 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* I2C_SCL */
200#endif
201#endif
202 /* PD13 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* TDM_STRB1 */
203 /* PD12 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* TDM_STRB2 */
204 /* PD11 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
205 /* PD10 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* BRGO4 (MCLK) */
206 /* PD9 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* SMC1_TX */
207 /* PD8 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* SMC1_RX */
208 /* PD7 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* N/C */
209 /* PD6 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* N/C */
210 /* PD5 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* N/C */
211 /* PD4 */ { CONF, SPEC, 1, DOUT, ACTV, 1 }, /* SMC2_RX */
212 /* PD3 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */
213 /* PD2 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */
214 /* PD1 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */
215 /* PD0 */ { SKIP, GPIO, 0, DIN, ACTV, 0 } /* pin doesn't exist */
216 }
217};