blob: 787ded0fe092abcce4fe07b3af990904026633f6 [file] [log] [blame]
Tom Warren112a1882011-04-14 12:18:06 +00001/*
2 * (C) Copyright 2010,2011
3 * NVIDIA Corporation <www.nvidia.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef _SCU_H_
25#define _SCU_H_
26
27/* ARM Snoop Control Unit (SCU) registers */
28struct scu_ctlr {
29 uint scu_ctrl; /* SCU Control Register, offset 00 */
30 uint scu_cfg; /* SCU Config Register, offset 04 */
31 uint scu_cpu_pwr_stat; /* SCU CPU Power Status Register, offset 08 */
32 uint scu_inv_all; /* SCU Invalidate All Register, offset 0C */
33 uint scu_reserved0[12]; /* reserved, offset 10-3C */
34 uint scu_filt_start; /* SCU Filtering Start Address Reg, offset 40 */
35 uint scu_filt_end; /* SCU Filtering End Address Reg, offset 44 */
36 uint scu_reserved1[2]; /* reserved, offset 48-4C */
37 uint scu_acc_ctl; /* SCU Access Control Register, offset 50 */
38 uint scu_ns_acc_ctl; /* SCU Non-secure Access Cntrl Reg, offset 54 */
39};
40
41#define SCU_CTRL_ENABLE (1 << 0)
42
43#endif /* SCU_H */