blob: 2c0d30a80ec118ed8f2ba7b7a52294a206adc2c1 [file] [log] [blame]
Paul Burton96c68472018-12-16 19:25:22 -03001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * JZ4780 DDR initialization - parameters definitions
4 *
5 * Copyright (c) 2015 Imagination Technologies
6 * Author: Matt Redfearn <matt.redfearn.com>
7 */
8
9#ifndef __JZ4780_DRAM_H__
10#define __JZ4780_DRAM_H__
11
12/*
13 * DDR
14 */
Simon Glass4dcacfc2020-05-10 11:40:13 -060015#include <linux/bitops.h>
Paul Burton96c68472018-12-16 19:25:22 -030016#define DDRC_ST 0x0
17#define DDRC_CFG 0x4
18#define DDRC_CTRL 0x8
19#define DDRC_LMR 0xc
20#define DDRC_REFCNT 0x18
21#define DDRC_DQS 0x1c
22#define DDRC_DQS_ADJ 0x20
23#define DDRC_MMAP0 0x24
24#define DDRC_MMAP1 0x28
25#define DDRC_MDELAY 0x2c
26#define DDRC_CKEL 0x30
27#define DDRC_PMEMCTRL0 0x54
28#define DDRC_PMEMCTRL1 0x50
29#define DDRC_PMEMCTRL2 0x58
30#define DDRC_PMEMCTRL3 0x5c
31
32#define DDRC_TIMING(n) (0x60 + 4 * (n))
33#define DDRC_REMMAP(n) (0x9c + 4 * (n))
34
35/*
36 * DDR PHY
37 */
38#define DDR_MEM_PHY_BASE 0x20000000
39#define DDR_PHY_OFFSET 0x1000
40
41#define DDRP_PIR 0x4
42#define DDRP_PGCR 0x8
43#define DDRP_PGSR 0xc
44
45#define DDRP_PTR0 0x18
46#define DDRP_PTR1 0x1c
47#define DDRP_PTR2 0x20
48
49#define DDRP_ACIOCR 0x24
50#define DDRP_DXCCR 0x28
51#define DDRP_DSGCR 0x2c
52#define DDRP_DCR 0x30
53
54#define DDRP_DTPR0 0x34
55#define DDRP_DTPR1 0x38
56#define DDRP_DTPR2 0x3c
57#define DDRP_MR0 0x40
58#define DDRP_MR1 0x44
59#define DDRP_MR2 0x48
60#define DDRP_MR3 0x4c
61
62#define DDRP_ODTCR 0x50
63#define DDRP_DTAR 0x54
64#define DDRP_DTDR0 0x58
65#define DDRP_DTDR1 0x5c
66
67#define DDRP_DCUAR 0xc0
68#define DDRP_DCUDR 0xc4
69#define DDRP_DCURR 0xc8
70#define DDRP_DCULR 0xcc
71#define DDRP_DCUGCR 0xd0
72#define DDRP_DCUTPR 0xd4
73#define DDRP_DCUSR0 0xd8
74#define DDRP_DCUSR1 0xdc
75
76#define DDRP_ZQXCR0(n) (0x180 + ((n) * 0x10))
77#define DDRP_ZQXCR1(n) (0x184 + ((n) * 0x10))
78#define DDRP_ZQXSR0(n) (0x188 + ((n) * 0x10))
79#define DDRP_ZQXSR1(n) (0x18c + ((n) * 0x10))
80
81#define DDRP_DXGCR(n) (0x1c0 + ((n) * 0x40))
82#define DDRP_DXGSR0(n) (0x1c4 + ((n) * 0x40))
83#define DDRP_DXGSR1(n) (0x1c8 + ((n) * 0x40))
84#define DDRP_DXDQSTR(n) (0x1d4 + ((n) * 0x40))
85
86/* DDRC Status Register */
87#define DDRC_ST_ENDIAN BIT(7)
88#define DDRC_ST_DPDN BIT(5)
89#define DDRC_ST_PDN BIT(4)
90#define DDRC_ST_AREF BIT(3)
91#define DDRC_ST_SREF BIT(2)
92#define DDRC_ST_CKE1 BIT(1)
93#define DDRC_ST_CKE0 BIT(0)
94
95/* DDRC Configure Register */
96#define DDRC_CFG_ROW1_BIT 27
97#define DDRC_CFG_ROW1_MASK (0x7 << DDRC_CFG_ROW1_BIT)
98#define DDRC_CFG_COL1_BIT 24
99#define DDRC_CFG_COL1_MASK (0x7 << DDRC_CFG_COL1_BIT)
100#define DDRC_CFG_BA1 BIT(23)
101#define DDRC_CFG_IMBA BIT(22)
102#define DDRC_CFG_BL_8 BIT(21)
103
104#define DDRC_CFG_TYPE_BIT 17
105#define DDRC_CFG_TYPE_MASK (0x7 << DDRC_CFG_TYPE_BIT)
106#define DDRC_CFG_TYPE_DDR1 (2 << DDRC_CFG_TYPE_BIT)
107#define DDRC_CFG_TYPE_MDDR (3 << DDRC_CFG_TYPE_BIT)
108#define DDRC_CFG_TYPE_DDR2 (4 << DDRC_CFG_TYPE_BIT)
109#define DDRC_CFG_TYPE_LPDDR2 (5 << DDRC_CFG_TYPE_BIT)
110#define DDRC_CFG_TYPE_DDR3 (6 << DDRC_CFG_TYPE_BIT)
111
112#define DDRC_CFG_ODT_EN BIT(16)
113
114#define DDRC_CFG_MPRT BIT(15)
115
116#define DDRC_CFG_ROW_BIT 11
117#define DDRC_CFG_ROW_MASK (0x7 << DDRC_CFG_ROW_BIT)
118#define DDRC_CFG_ROW_12 (0 << DDRC_CFG_ROW_BIT)
119#define DDRC_CFG_ROW_13 (1 << DDRC_CFG_ROW_BIT)
120#define DDRC_CFG_ROW_14 (2 << DDRC_CFG_ROW_BIT)
121
122#define DDRC_CFG_COL_BIT 8
123#define DDRC_CFG_COL_MASK (0x7 << DDRC_CFG_COL_BIT)
124#define DDRC_CFG_COL_8 (0 << DDRC_CFG_COL_BIT)
125#define DDRC_CFG_COL_9 (1 << DDRC_CFG_COL_BIT)
126#define DDRC_CFG_COL_10 (2 << DDRC_CFG_COL_BIT)
127#define DDRC_CFG_COL_11 (3 << DDRC_CFG_COL_BIT)
128
129#define DDRC_CFG_CS1EN BIT(7)
130#define DDRC_CFG_CS0EN BIT(6)
131#define DDRC_CFG_CL_BIT 2
132#define DDRC_CFG_CL_MASK (0xf << DDRC_CFG_CL_BIT)
133#define DDRC_CFG_CL_3 (0 << DDRC_CFG_CL_BIT)
134#define DDRC_CFG_CL_4 (1 << DDRC_CFG_CL_BIT)
135#define DDRC_CFG_CL_5 (2 << DDRC_CFG_CL_BIT)
136#define DDRC_CFG_CL_6 (3 << DDRC_CFG_CL_BIT)
137
138#define DDRC_CFG_BA BIT(1)
139#define DDRC_CFG_DW BIT(0)
140
141/* DDRC Control Register */
142#define DDRC_CTRL_DFI_RST BIT(23)
143#define DDRC_CTRL_DLL_RST BIT(22)
144#define DDRC_CTRL_CTL_RST BIT(21)
145#define DDRC_CTRL_CFG_RST BIT(20)
146#define DDRC_CTRL_ACTPD BIT(15)
147#define DDRC_CTRL_PDT_BIT 12
148#define DDRC_CTRL_PDT_MASK (0x7 << DDRC_CTRL_PDT_BIT)
149#define DDRC_CTRL_PDT_DIS (0 << DDRC_CTRL_PDT_BIT)
150#define DDRC_CTRL_PDT_8 (1 << DDRC_CTRL_PDT_BIT)
151#define DDRC_CTRL_PDT_16 (2 << DDRC_CTRL_PDT_BIT)
152#define DDRC_CTRL_PDT_32 (3 << DDRC_CTRL_PDT_BIT)
153#define DDRC_CTRL_PDT_64 (4 << DDRC_CTRL_PDT_BIT)
154#define DDRC_CTRL_PDT_128 (5 << DDRC_CTRL_PDT_BIT)
155
156#define DDRC_CTRL_PRET_BIT 8
157#define DDRC_CTRL_PRET_MASK (0x7 << DDRC_CTRL_PRET_BIT)
158#define DDRC_CTRL_PRET_DIS (0 << DDRC_CTRL_PRET_BIT)
159#define DDRC_CTRL_PRET_8 (1 << DDRC_CTRL_PRET_BIT)
160#define DDRC_CTRL_PRET_16 (2 << DDRC_CTRL_PRET_BIT)
161#define DDRC_CTRL_PRET_32 (3 << DDRC_CTRL_PRET_BIT)
162#define DDRC_CTRL_PRET_64 (4 << DDRC_CTRL_PRET_BIT)
163#define DDRC_CTRL_PRET_128 (5 << DDRC_CTRL_PRET_BIT)
164
165#define DDRC_CTRL_DPD BIT(6)
166#define DDRC_CTRL_SR BIT(5)
167#define DDRC_CTRL_UNALIGN BIT(4)
168#define DDRC_CTRL_ALH BIT(3)
169#define DDRC_CTRL_RDC BIT(2)
170#define DDRC_CTRL_CKE BIT(1)
171#define DDRC_CTRL_RESET BIT(0)
172
173/* DDRC Load-Mode-Register */
174#define DDRC_LMR_DDR_ADDR_BIT 16
175#define DDRC_LMR_DDR_ADDR_MASK (0x3fff << DDRC_LMR_DDR_ADDR_BIT)
176
177#define DDRC_LMR_BA_BIT 8
178#define DDRC_LMR_BA_MASK (0x7 << DDRC_LMR_BA_BIT)
179/* For DDR2 */
180#define DDRC_LMR_BA_MRS (0 << DDRC_LMR_BA_BIT)
181#define DDRC_LMR_BA_EMRS1 (1 << DDRC_LMR_BA_BIT)
182#define DDRC_LMR_BA_EMRS2 (2 << DDRC_LMR_BA_BIT)
183#define DDRC_LMR_BA_EMRS3 (3 << DDRC_LMR_BA_BIT)
184/* For mobile DDR */
185#define DDRC_LMR_BA_M_MRS (0 << DDRC_LMR_BA_BIT)
186#define DDRC_LMR_BA_M_EMRS (2 << DDRC_LMR_BA_BIT)
187#define DDRC_LMR_BA_M_SR (1 << DDRC_LMR_BA_BIT)
188/* For Normal DDR1 */
189#define DDRC_LMR_BA_N_MRS (0 << DDRC_LMR_BA_BIT)
190#define DDRC_LMR_BA_N_EMRS (1 << DDRC_LMR_BA_BIT)
191
192#define DDRC_LMR_CMD_BIT 4
193#define DDRC_LMR_CMD_MASK (0x3 << DDRC_LMR_CMD_BIT)
194#define DDRC_LMR_CMD_PREC (0 << DDRC_LMR_CMD_BIT)
195#define DDRC_LMR_CMD_AUREF (1 << DDRC_LMR_CMD_BIT)
196#define DDRC_LMR_CMD_LMR (2 << DDRC_LMR_CMD_BIT)
197
198#define DDRC_LMR_START BIT(0)
199
200/* DDRC Timing Config Register 1 */
201#define DDRC_TIMING1_TRTP_BIT 24
202#define DDRC_TIMING1_TRTP_MASK (0x3f << DDRC_TIMING1_TRTP_BIT)
203#define DDRC_TIMING1_TWTR_BIT 16
204#define DDRC_TIMING1_TWTR_MASK (0x3f << DDRC_TIMING1_TWTR_BIT)
205#define DDRC_TIMING1_TWTR_1 (0 << DDRC_TIMING1_TWTR_BIT)
206#define DDRC_TIMING1_TWTR_2 (1 << DDRC_TIMING1_TWTR_BIT)
207#define DDRC_TIMING1_TWTR_3 (2 << DDRC_TIMING1_TWTR_BIT)
208#define DDRC_TIMING1_TWTR_4 (3 << DDRC_TIMING1_TWTR_BIT)
209#define DDRC_TIMING1_TWR_BIT 8
210#define DDRC_TIMING1_TWR_MASK (0x3f << DDRC_TIMING1_TWR_BIT)
211#define DDRC_TIMING1_TWR_1 (0 << DDRC_TIMING1_TWR_BIT)
212#define DDRC_TIMING1_TWR_2 (1 << DDRC_TIMING1_TWR_BIT)
213#define DDRC_TIMING1_TWR_3 (2 << DDRC_TIMING1_TWR_BIT)
214#define DDRC_TIMING1_TWR_4 (3 << DDRC_TIMING1_TWR_BIT)
215#define DDRC_TIMING1_TWR_5 (4 << DDRC_TIMING1_TWR_BIT)
216#define DDRC_TIMING1_TWR_6 (5 << DDRC_TIMING1_TWR_BIT)
217#define DDRC_TIMING1_TWL_BIT 0
218#define DDRC_TIMING1_TWL_MASK (0x3f << DDRC_TIMING1_TWL_BIT)
219
220/* DDRC Timing Config Register 2 */
221#define DDRC_TIMING2_TCCD_BIT 24
222#define DDRC_TIMING2_TCCD_MASK (0x3f << DDRC_TIMING2_TCCD_BIT)
223#define DDRC_TIMING2_TRAS_BIT 16
224#define DDRC_TIMING2_TRAS_MASK (0x3f << DDRC_TIMING2_TRAS_BIT)
225#define DDRC_TIMING2_TRCD_BIT 8
226#define DDRC_TIMING2_TRCD_MASK (0x3f << DDRC_TIMING2_TRCD_BIT)
227#define DDRC_TIMING2_TRL_BIT 0
228#define DDRC_TIMING2_TRL_MASK (0x3f << DDRC_TIMING2_TRL_BIT)
229
230/* DDRC Timing Config Register 3 */
231#define DDRC_TIMING3_ONUM 27
232#define DDRC_TIMING3_TCKSRE_BIT 24
233#define DDRC_TIMING3_TCKSRE_MASK (0x3f << DDRC_TIMING3_TCKSRE_BIT)
234#define DDRC_TIMING3_TRP_BIT 16
235#define DDRC_TIMING3_TRP_MASK (0x3f << DDRC_TIMING3_TRP_BIT)
236#define DDRC_TIMING3_TRRD_BIT 8
237#define DDRC_TIMING3_TRRD_MASK (0x3f << DDRC_TIMING3_TRRD_BIT)
238#define DDRC_TIMING3_TRRD_DISABLE (0 << DDRC_TIMING3_TRRD_BIT)
239#define DDRC_TIMING3_TRRD_2 (1 << DDRC_TIMING3_TRRD_BIT)
240#define DDRC_TIMING3_TRRD_3 (2 << DDRC_TIMING3_TRRD_BIT)
241#define DDRC_TIMING3_TRRD_4 (3 << DDRC_TIMING3_TRRD_BIT)
242#define DDRC_TIMING3_TRC_BIT 0
243#define DDRC_TIMING3_TRC_MASK (0x3f << DDRC_TIMING3_TRC_BIT)
244
245/* DDRC Timing Config Register 4 */
246#define DDRC_TIMING4_TRFC_BIT 24
247#define DDRC_TIMING4_TRFC_MASK (0x3f << DDRC_TIMING4_TRFC_BIT)
248#define DDRC_TIMING4_TEXTRW_BIT 21
249#define DDRC_TIMING4_TEXTRW_MASK (0x7 << DDRC_TIMING4_TEXTRW_BIT)
250#define DDRC_TIMING4_TRWCOV_BIT 19
251#define DDRC_TIMING4_TRWCOV_MASK (0x3 << DDRC_TIMING4_TRWCOV_BIT)
252#define DDRC_TIMING4_TCKE_BIT 16
253#define DDRC_TIMING4_TCKE_MASK (0x7 << DDRC_TIMING4_TCKE_BIT)
254#define DDRC_TIMING4_TMINSR_BIT 8
255#define DDRC_TIMING4_TMINSR_MASK (0xf << DDRC_TIMING4_TMINSR_BIT)
256#define DDRC_TIMING4_TXP_BIT 4
257#define DDRC_TIMING4_TXP_MASK (0x7 << DDRC_TIMING4_TXP_BIT)
258#define DDRC_TIMING4_TMRD_BIT 0
259#define DDRC_TIMING4_TMRD_MASK (0x3 << DDRC_TIMING4_TMRD_BIT)
260
261/* DDRC Timing Config Register 5 */
262#define DDRC_TIMING5_TCTLUPD_BIT 24
263#define DDRC_TIMING4_TCTLUPD_MASK (0x3f << DDRC_TIMING5_TCTLUDP_BIT)
264#define DDRC_TIMING5_TRTW_BIT 16
265#define DDRC_TIMING5_TRTW_MASK (0x3f << DDRC_TIMING5_TRTW_BIT)
266#define DDRC_TIMING5_TRDLAT_BIT 8
267#define DDRC_TIMING5_TRDLAT_MASK (0x3f << DDRC_TIMING5_TRDLAT_BIT)
268#define DDRC_TIMING5_TWDLAT_BIT 0
269#define DDRC_TIMING5_TWDLAT_MASK (0x3f << DDRC_TIMING5_TWDLAT_BIT)
270
271/* DDRC Timing Config Register 6 */
272#define DDRC_TIMING6_TXSRD_BIT 24
273#define DDRC_TIMING6_TXSRD_MASK (0x3f << DDRC_TIMING6_TXSRD_BIT)
274#define DDRC_TIMING6_TFAW_BIT 16
275#define DDRC_TIMING6_TFAW_MASK (0x3f << DDRC_TIMING6_TFAW_BIT)
276#define DDRC_TIMING6_TCFGW_BIT 8
277#define DDRC_TIMING6_TCFGW_MASK (0x3f << DDRC_TIMING6_TCFGW_BIT)
278#define DDRC_TIMING6_TCFGR_BIT 0
279#define DDRC_TIMING6_TCFGR_MASK (0x3f << DDRC_TIMING6_TCFGR_BIT)
280
281/* DDRC Auto-Refresh Counter */
282#define DDRC_REFCNT_CON_BIT 16
283#define DDRC_REFCNT_CON_MASK (0xff << DDRC_REFCNT_CON_BIT)
284#define DDRC_REFCNT_CNT_BIT 8
285#define DDRC_REFCNT_CNT_MASK (0xff << DDRC_REFCNT_CNT_BIT)
286#define DDRC_REFCNT_CLKDIV_BIT 1
287#define DDRC_REFCNT_CLKDIV_MASK (0x7 << DDRC_REFCNT_CLKDIV_BIT)
288#define DDRC_REFCNT_REF_EN BIT(0)
289
290/* DDRC DQS Delay Control Register */
291#define DDRC_DQS_ERROR BIT(29)
292#define DDRC_DQS_READY BIT(28)
293#define DDRC_DQS_AUTO BIT(23)
294#define DDRC_DQS_DET BIT(24)
295#define DDRC_DQS_SRDET BIT(25)
296#define DDRC_DQS_CLKD_BIT 16
297#define DDRC_DQS_CLKD_MASK (0x3f << DDRC_DQS_CLKD_BIT)
298#define DDRC_DQS_WDQS_BIT 8
299#define DDRC_DQS_WDQS_MASK (0x3f << DDRC_DQS_WDQS_BIT)
300#define DDRC_DQS_RDQS_BIT 0
301#define DDRC_DQS_RDQS_MASK (0x3f << DDRC_DQS_RDQS_BIT)
302
303/* DDRC DQS Delay Adjust Register */
304#define DDRC_DQS_ADJWDQS_BIT 8
305#define DDRC_DQS_ADJWDQS_MASK (0x1f << DDRC_DQS_ADJWDQS_BIT)
306#define DDRC_DQS_ADJRDQS_BIT 0
307#define DDRC_DQS_ADJRDQS_MASK (0x1f << DDRC_DQS_ADJRDQS_BIT)
308
309/* DDRC Memory Map Config Register */
310#define DDRC_MMAP_BASE_BIT 8
311#define DDRC_MMAP_BASE_MASK (0xff << DDRC_MMAP_BASE_BIT)
312#define DDRC_MMAP_MASK_BIT 0
313#define DDRC_MMAP_MASK_MASK (0xff << DDRC_MMAP_MASK_BIT)
314
315#define DDRC_MMAP0_BASE (0x20 << DDRC_MMAP_BASE_BIT)
316#define DDRC_MMAP1_BASE_64M (0x24 << DDRC_MMAP_BASE_BIT)
317#define DDRC_MMAP1_BASE_128M (0x28 << DDRC_MMAP_BASE_BIT)
318#define DDRC_MMAP1_BASE_256M (0x30 << DDRC_MMAP_BASE_BIT)
319
320#define DDRC_MMAP_MASK_64_64 (0xfc << DDRC_MMAP_MASK_BIT)
321#define DDRC_MMAP_MASK_128_128 (0xf8 << DDRC_MMAP_MASK_BIT)
322#define DDRC_MMAP_MASK_256_256 (0xf0 << DDRC_MMAP_MASK_BIT)
323
324/* DDRP PHY Initialization Register */
325#define DDRP_PIR_INIT BIT(0)
326#define DDRP_PIR_DLLSRST BIT(1)
327#define DDRP_PIR_DLLLOCK BIT(2)
328#define DDRP_PIR_ZCAL BIT(3)
329#define DDRP_PIR_ITMSRST BIT(4)
330#define DDRP_PIR_DRAMRST BIT(5)
331#define DDRP_PIR_DRAMINT BIT(6)
332#define DDRP_PIR_QSTRN BIT(7)
333#define DDRP_PIR_EYETRN BIT(8)
334#define DDRP_PIR_DLLBYP BIT(17)
335/* DDRP PHY General Configurate Register */
336#define DDRP_PGCR_ITMDMD BIT(0)
337#define DDRP_PGCR_DQSCFG BIT(1)
338#define DDRP_PGCR_DFTCMP BIT(2)
339#define DDRP_PGCR_DFTLMT_BIT 3
340#define DDRP_PGCR_DTOSEL_BIT 5
341#define DDRP_PGCR_CKEN_BIT 9
342#define DDRP_PGCR_CKDV_BIT 12
343#define DDRP_PGCR_CKINV BIT(14)
344#define DDRP_PGCR_RANKEN_BIT 18
345#define DDRP_PGCR_ZCKSEL_32 (2 << 22)
346#define DDRP_PGCR_PDDISDX BIT(24)
347/* DDRP PHY General Status Register */
348#define DDRP_PGSR_IDONE BIT(0)
349#define DDRP_PGSR_DLDONE BIT(1)
350#define DDRP_PGSR_ZCDONE BIT(2)
351#define DDRP_PGSR_DIDONE BIT(3)
352#define DDRP_PGSR_DTDONE BIT(4)
353#define DDRP_PGSR_DTERR BIT(5)
354#define DDRP_PGSR_DTIERR BIT(6)
355#define DDRP_PGSR_DFTEERR BIT(7)
356/* DDRP DRAM Configuration Register */
357#define DDRP_DCR_TYPE_BIT 0
358#define DDRP_DCR_TYPE_MASK (0x7 << DDRP_DCR_TYPE_BIT)
359#define DDRP_DCR_TYPE_MDDR (0 << DDRP_DCR_TYPE_BIT)
360#define DDRP_DCR_TYPE_DDR (1 << DDRP_DCR_TYPE_BIT)
361#define DDRP_DCR_TYPE_DDR2 (2 << DDRP_DCR_TYPE_BIT)
362#define DDRP_DCR_TYPE_DDR3 (3 << DDRP_DCR_TYPE_BIT)
363#define DDRP_DCR_TYPE_LPDDR2 (4 << DDRP_DCR_TYPE_BIT)
364#define DDRP_DCR_DDR8BNK_BIT 3
365#define DDRP_DCR_DDR8BNK_MASK (1 << DDRP_DCR_DDR8BNK_BIT)
366#define DDRP_DCR_DDR8BNK (1 << DDRP_DCR_DDR8BNK_BIT)
367#define DDRP_DCR_DDR8BNK_DIS (0 << DDRP_DCR_DDR8BNK_BIT)
368
369#define DRP_DTRP1_RTODT BIT(11)
370
371#define DDRP_DXGCR_DXEN BIT(0)
372
373#define DDRP_ZQXCR_ZDEN_BIT 28
374#define DDRP_ZQXCR_ZDEN (1 << DDRP_ZQXCR_ZDEN_BIT)
375#define DDRP_ZQXCR_PULLUP_IMPE_BIT 5
376#define DDRP_ZQXCR_PULLDOWN_IMPE_BIT 0
377
378/* DDR3 Mode Register Set */
379#define DDR3_MR0_BL_BIT 0
380#define DDR3_MR0_BL_MASK (3 << DDR3_MR0_BL_BIT)
381#define DDR3_MR0_BL_8 (0 << DDR3_MR0_BL_BIT)
382#define DDR3_MR0_BL_fly (1 << DDR3_MR0_BL_BIT)
383#define DDR3_MR0_BL_4 (2 << DDR3_MR0_BL_BIT)
384#define DDR3_MR0_BT_BIT 3
385#define DDR3_MR0_BT_MASK (1 << DDR3_MR0_BT_BIT)
386#define DDR3_MR0_BT_SEQ (0 << DDR3_MR0_BT_BIT)
387#define DDR3_MR0_BT_INTER (1 << DDR3_MR0_BT_BIT)
388#define DDR3_MR0_WR_BIT 9
389
390#define DDR3_MR1_DLL_DISABLE 1
391#define DDR3_MR1_DIC_6 (0 << 5 | 0 << 1)
392#define DDR3_MR1_DIC_7 (0 << 5 | BIT(1))
393#define DDR3_MR1_RTT_DIS (0 << 9 | 0 << 6 | 0 << 2)
394#define DDR3_MR1_RTT_4 (0 << 9 | 0 << 6 | BIT(2))
395#define DDR3_MR1_RTT_2 (0 << 9 | BIT(6) | 0 << 2)
396#define DDR3_MR1_RTT_6 (0 << 9 | BIT(6) | BIT(2))
397#define DDR3_MR1_RTT_12 (BIT(9) | 0 << 6 | 0 << 2)
398#define DDR3_MR1_RTT_8 (BIT(9) | 0 << 6 | BIT(2))
399
400#define DDR3_MR2_CWL_BIT 3
401
402/* Parameters common to all RAM devices used */
403
404/* Chip Select */
405/* CSEN : whether a ddr chip exists 0 - un-used, 1 - used */
406#define DDR_CS0EN 1
407/* CSEN : whether a ddr chip exists 0 - un-used, 1 - used */
408#define DDR_CS1EN 0
409
410/* ROW : 12 to 18 row address, 1G only 512MB */
411#define DDR_ROW 15
412/* COL : 8 to 14 column address */
413#define DDR_COL 10
414/* Banks each chip: 0-4bank, 1-8bank */
415#define DDR_BANK8 1
416/* 0 - 16-bit data width, 1 - 32-bit data width */
417#define DDR_DW32 1
418
419/* Refresh period: 64ms / 32768 = 1.95 us , 2 ^ 15 = 32768 */
420#define DDR_tREFI 7800
421/* Clock Divider */
422#define DDR_CLK_DIV 1
423
424/* DDR3 Burst length: 0 - 8 burst, 2 - 4 burst , 1 - 4 or 8 (on the fly) */
425#define DDR_BL 8
426
427/* CAS latency: 5 to 14, tCK */
428#define DDR_CL 6
429/* DDR3 only: CAS Write Latency, 5 to 8 */
430#define DDR_tCWL (DDR_CL - 1)
431
432/* Structure representing per-RAM type configuration */
433
434struct jz4780_ddr_config {
435 u32 timing[6]; /* Timing1..6 register value */
436
437 /* DDR PHY control */
438 u16 mr0; /* Mode Register 0 */
439 u16 mr1; /* Mode Register 1 */
440
441 u32 ptr0; /* PHY Timing Register 0 */
442 u32 ptr1; /* PHY Timing Register 1 */
443 u32 ptr2; /* PHY Timing Register 1 */
444
445 u32 dtpr0; /* DRAM Timing Parameters Register 0 */
446 u32 dtpr1; /* DRAM Timing Parameters Register 1 */
447 u32 dtpr2; /* DRAM Timing Parameters Register 2 */
448
449 u8 pullup; /* PHY pullup impedance */
450 u8 pulldn; /* PHY pulldown impedance */
451};
452
453void pll_init(void);
454void sdram_init(void);
455
456#endif /* __JZ4780_DRAM_H__ */