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git01.mediatek.com / filogic / uboot / 07c23fd23ddc39f8d4ccc29f74fc6be89c295d6a / . / drivers / pinctrl / qcom / pinctrl-ipq9574.c
blob: ce09072ae3c55768171e13b53637f072d6420064 [file] [log] [blame]
Varadarajan Narayanan44891d52025-02-26 12:15:03 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * pinctrl driver for Qualcomm ipq9574
4 *
5 * (C) Copyright 2025 Linaro Ltd.
6 */
7
8#include <dm.h>
9
10#include "pinctrl-qcom.h"
11
12#define MAX_PIN_NAME_LEN 32
13static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
14
15enum ipq9574_functions {
16 msm_mux_blsp0_spi,
17 msm_mux_blsp0_uart,
18 msm_mux_blsp1_i2c,
19 msm_mux_blsp1_spi,
20 msm_mux_blsp1_uart,
21 msm_mux_blsp2_i2c,
22 msm_mux_blsp2_spi,
23 msm_mux_blsp2_uart,
24 msm_mux_blsp3_i2c,
25 msm_mux_blsp3_spi,
26 msm_mux_blsp3_uart,
27 msm_mux_blsp4_i2c,
28 msm_mux_blsp4_spi,
29 msm_mux_blsp4_uart,
30 msm_mux_blsp5_i2c,
31 msm_mux_blsp5_uart,
32 msm_mux_gpio,
33 msm_mux_mdc,
34 msm_mux_mdio,
35 msm_mux_pcie0_clk,
36 msm_mux_pcie0_wake,
37 msm_mux_pcie1_clk,
38 msm_mux_pcie1_wake,
39 msm_mux_pcie2_clk,
40 msm_mux_pcie2_wake,
41 msm_mux_pcie3_clk,
42 msm_mux_pcie3_wake,
43 msm_mux_qspi_data,
44 msm_mux_qspi_clk,
45 msm_mux_qspi_cs,
46 msm_mux_sdc_data,
47 msm_mux_sdc_clk,
48 msm_mux_sdc_cmd,
49 msm_mux_sdc_rclk,
50 msm_mux_NA,
51};
52
53#define MSM_PIN_FUNCTION(fname) \
54 [msm_mux_##fname] = {#fname, msm_mux_##fname}
55
56static const struct pinctrl_function msm_pinctrl_functions[] = {
57 MSM_PIN_FUNCTION(blsp0_spi),
58 MSM_PIN_FUNCTION(blsp0_uart),
59 MSM_PIN_FUNCTION(blsp1_i2c),
60 MSM_PIN_FUNCTION(blsp1_spi),
61 MSM_PIN_FUNCTION(blsp1_uart),
62 MSM_PIN_FUNCTION(blsp2_i2c),
63 MSM_PIN_FUNCTION(blsp2_spi),
64 MSM_PIN_FUNCTION(blsp2_uart),
65 MSM_PIN_FUNCTION(blsp3_i2c),
66 MSM_PIN_FUNCTION(blsp3_spi),
67 MSM_PIN_FUNCTION(blsp3_uart),
68 MSM_PIN_FUNCTION(blsp4_i2c),
69 MSM_PIN_FUNCTION(blsp4_spi),
70 MSM_PIN_FUNCTION(blsp4_uart),
71 MSM_PIN_FUNCTION(blsp5_i2c),
72 MSM_PIN_FUNCTION(blsp5_uart),
73 MSM_PIN_FUNCTION(gpio),
74 MSM_PIN_FUNCTION(mdc),
75 MSM_PIN_FUNCTION(mdio),
76 MSM_PIN_FUNCTION(pcie0_clk),
77 MSM_PIN_FUNCTION(pcie0_wake),
78 MSM_PIN_FUNCTION(pcie1_clk),
79 MSM_PIN_FUNCTION(pcie1_wake),
80 MSM_PIN_FUNCTION(pcie2_clk),
81 MSM_PIN_FUNCTION(pcie2_wake),
82 MSM_PIN_FUNCTION(pcie3_clk),
83 MSM_PIN_FUNCTION(pcie3_wake),
84 MSM_PIN_FUNCTION(qspi_data),
85 MSM_PIN_FUNCTION(qspi_clk),
86 MSM_PIN_FUNCTION(qspi_cs),
87 MSM_PIN_FUNCTION(sdc_data),
88 MSM_PIN_FUNCTION(sdc_clk),
89 MSM_PIN_FUNCTION(sdc_cmd),
90 MSM_PIN_FUNCTION(sdc_rclk),
91};
92
93typedef unsigned int msm_pin_function[10];
94
95#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
96 [id] = { msm_mux_gpio, /* gpio mode */ \
97 msm_mux_##f1, \
98 msm_mux_##f2, \
99 msm_mux_##f3, \
100 msm_mux_##f4, \
101 msm_mux_##f5, \
102 msm_mux_##f6, \
103 msm_mux_##f7, \
104 msm_mux_##f8, \
105 msm_mux_##f9, \
106 }
107
108static const msm_pin_function ipq9574_pin_functions[] = {
109 PINGROUP(0, sdc_data, qspi_data, NA, NA, NA, NA, NA, NA, NA),
110 PINGROUP(1, sdc_data, qspi_data, NA, NA, NA, NA, NA, NA, NA),
111 PINGROUP(2, sdc_data, qspi_data, NA, NA, NA, NA, NA, NA, NA),
112 PINGROUP(3, sdc_data, qspi_data, NA, NA, NA, NA, NA, NA, NA),
113 PINGROUP(4, sdc_cmd, qspi_cs, NA, NA, NA, NA, NA, NA, NA),
114 PINGROUP(5, sdc_clk, qspi_clk, NA, NA, NA, NA, NA, NA, NA),
115 PINGROUP(6, sdc_data, NA, NA, NA, NA, NA, NA, NA, NA),
116 PINGROUP(7, sdc_data, NA, NA, NA, NA, NA, NA, NA, NA),
117 PINGROUP(8, sdc_data, NA, NA, NA, NA, NA, NA, NA, NA),
118 PINGROUP(9, sdc_data, NA, NA, NA, NA, NA, NA, NA, NA),
119 PINGROUP(10, sdc_rclk, NA, NA, NA, NA, NA, NA, NA, NA),
120 PINGROUP(11, blsp0_spi, blsp0_uart, NA, NA, NA, NA, NA, NA, NA),
121 PINGROUP(12, blsp0_spi, blsp0_uart, NA, NA, NA, NA, NA, NA, NA),
122 PINGROUP(13, blsp0_spi, blsp0_uart, NA, NA, NA, NA, NA, NA, NA),
123 PINGROUP(14, blsp0_spi, blsp0_uart, NA, NA, NA, NA, NA, NA, NA),
124 PINGROUP(15, blsp3_spi, blsp3_i2c, blsp3_uart, NA, NA, NA, NA, NA, NA),
125 PINGROUP(16, blsp3_spi, blsp3_i2c, blsp3_uart, NA, NA, NA, NA, NA, NA),
126 PINGROUP(17, blsp3_spi, blsp3_uart, NA, NA, NA, NA, NA, NA, NA),
127 PINGROUP(18, blsp3_spi, blsp3_uart, NA, NA, NA, NA, NA, NA, NA),
128 PINGROUP(19, blsp3_spi, NA, NA, NA, NA, NA, NA, NA, NA),
129 PINGROUP(20, blsp3_spi, NA, NA, NA, NA, NA, NA, NA, NA),
130 PINGROUP(21, blsp3_spi, NA, NA, NA, NA, NA, NA, NA, NA),
131 PINGROUP(22, pcie0_clk, NA, NA, NA, NA, NA, NA, NA, NA),
132 PINGROUP(23, NA, NA, NA, NA, NA, NA, NA, NA, NA),
133 PINGROUP(24, pcie0_wake, NA, NA, NA, NA, NA, NA, NA, NA),
134 PINGROUP(25, pcie1_clk, NA, NA, NA, NA, NA, NA, NA, NA),
135 PINGROUP(26, NA, NA, NA, NA, NA, NA, NA, NA, NA),
136 PINGROUP(27, pcie1_wake, NA, NA, NA, NA, NA, NA, NA, NA),
137 PINGROUP(28, pcie2_clk, NA, NA, NA, NA, NA, NA, NA, NA),
138 PINGROUP(29, NA, NA, NA, NA, NA, NA, NA, NA, NA),
139 PINGROUP(30, pcie2_wake, NA, NA, NA, NA, NA, NA, NA, NA),
140 PINGROUP(31, pcie3_clk, NA, NA, NA, NA, NA, NA, NA, NA),
141 PINGROUP(32, NA, NA, NA, NA, NA, NA, NA, NA, NA),
142 PINGROUP(33, pcie3_wake, NA, NA, NA, NA, NA, NA, NA, NA),
143 PINGROUP(34, blsp2_uart, blsp2_i2c, blsp2_spi, blsp1_uart, NA, NA, NA, NA, NA),
144 PINGROUP(35, blsp2_uart, blsp2_i2c, blsp2_spi, blsp1_uart, NA, NA, NA, NA, NA),
145 PINGROUP(36, blsp1_uart, blsp1_i2c, blsp2_spi, NA, NA, NA, NA, NA, NA),
146 PINGROUP(37, blsp1_uart, blsp1_i2c, blsp2_spi, NA, NA, NA, NA, NA, NA),
147 PINGROUP(38, mdc, NA, NA, NA, NA, NA, NA, NA, NA),
148 PINGROUP(39, mdio, NA, NA, NA, NA, NA, NA, NA, NA),
149 PINGROUP(40, NA, NA, NA, NA, NA, NA, NA, NA, NA),
150 PINGROUP(41, NA, NA, NA, NA, NA, NA, NA, NA, NA),
151 PINGROUP(42, NA, NA, NA, NA, NA, NA, NA, NA, NA),
152 PINGROUP(43, NA, NA, NA, NA, NA, NA, NA, NA, NA),
153 PINGROUP(44, NA, NA, NA, NA, NA, NA, NA, NA, NA),
154 PINGROUP(45, NA, NA, NA, NA, NA, NA, NA, NA, NA),
155 PINGROUP(46, NA, NA, NA, NA, NA, NA, NA, NA, NA),
156 PINGROUP(47, NA, NA, NA, NA, NA, NA, NA, NA, NA),
157 PINGROUP(48, blsp5_i2c, blsp5_uart, NA, NA, NA, NA, NA, NA, NA),
158 PINGROUP(49, blsp5_i2c, blsp5_uart, NA, NA, NA, NA, NA, NA, NA),
159 PINGROUP(50, blsp4_uart, blsp4_i2c, blsp4_spi, NA, NA, NA, NA, NA, NA),
160 PINGROUP(51, blsp4_uart, blsp4_i2c, blsp4_spi, NA, NA, NA, NA, NA, NA),
161 PINGROUP(52, blsp4_uart, blsp4_spi, NA, NA, NA, NA, NA, NA, NA),
162 PINGROUP(53, blsp4_uart, blsp4_spi, NA, NA, NA, NA, NA, NA, NA),
163 PINGROUP(54, NA, NA, NA, NA, NA, NA, NA, NA, NA),
164 PINGROUP(55, NA, NA, NA, NA, NA, NA, NA, NA, NA),
165 PINGROUP(56, NA, NA, NA, NA, NA, NA, NA, NA, NA),
166 PINGROUP(57, NA, NA, NA, NA, NA, NA, NA, NA, NA),
167 PINGROUP(58, NA, NA, NA, NA, NA, NA, NA, NA, NA),
168 PINGROUP(59, NA, NA, NA, NA, NA, NA, NA, NA, NA),
169 PINGROUP(60, NA, NA, NA, NA, NA, NA, NA, NA, NA),
170 PINGROUP(61, blsp1_spi, NA, NA, NA, NA, NA, NA, NA, NA),
171 PINGROUP(62, blsp1_spi, NA, NA, NA, NA, NA, NA, NA, NA),
172 PINGROUP(63, blsp1_spi, NA, NA, NA, NA, NA, NA, NA, NA),
173 PINGROUP(64, blsp1_spi, NA, NA, NA, NA, NA, NA, NA, NA),
174};
175
176static const char *ipq9574_get_function_name(struct udevice *dev,
177 unsigned int selector)
178{
179 return msm_pinctrl_functions[selector].name;
180}
181
182static const char *ipq9574_get_pin_name(struct udevice *dev,
183 unsigned int selector)
184{
185 snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
186 return pin_name;
187}
188
189static int ipq9574_get_function_mux(unsigned int pin, unsigned int selector)
190{
191 unsigned int i;
192 const msm_pin_function *func = ipq9574_pin_functions + pin;
193
194 for (i = 0; i < 10; i++)
195 if ((*func)[i] == selector)
196 return i;
197
198 debug("Can't find requested function for pin:selector %u:%u\n",
199 pin, selector);
200
201 return -EINVAL;
202}
203
204static const struct msm_pinctrl_data ipq9574_data = {
205 .pin_data = {
206 .pin_count = 65,
207 },
208 .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
209 .get_function_name = ipq9574_get_function_name,
210 .get_function_mux = ipq9574_get_function_mux,
211 .get_pin_name = ipq9574_get_pin_name,
212};
213
214static const struct udevice_id msm_pinctrl_ids[] = {
215 { .compatible = "qcom,ipq9574-tlmm", .data = (ulong)&ipq9574_data },
216 { /* Sentinal */ }
217};
218
219U_BOOT_DRIVER(pinctrl_ipq9574) = {
220 .name = "pinctrl_ipq9574",
221 .id = UCLASS_NOP,
222 .of_match = msm_pinctrl_ids,
223 .ops = &msm_pinctrl_ops,
224 .bind = msm_pinctrl_bind,
225 .flags = DM_FLAG_PRE_RELOC,
226};