blob: d691f135e89ce6924ab297eab7018ffc84947ff0 [file] [log] [blame]
Siva Durga Prasad Paladugub7398972019-08-05 15:54:59 +05301// SPDX-License-Identifier: GPL-2.0
2/*
3 * (C) Copyright 2019, Xilinx, Inc,
Michal Simeka8c94362023-07-10 14:35:49 +02004 * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
Siva Durga Prasad Paladugub7398972019-08-05 15:54:59 +05305 */
6
Simon Glass63334482019-11-14 12:57:39 -07007#include <cpu_func.h>
Simon Glass0f2af882020-05-10 11:40:05 -06008#include <log.h>
Siva Durga Prasad Paladugub7398972019-08-05 15:54:59 +05309#include <asm/arch/sys_proto.h>
10#include <memalign.h>
11#include <versalpl.h>
Michal Simek81efd2a2019-10-04 15:45:29 +020012#include <zynqmp_firmware.h>
Simon Glass274e0b02020-05-10 11:39:56 -060013#include <asm/cache.h>
Siva Durga Prasad Paladugub7398972019-08-05 15:54:59 +053014
15static ulong versal_align_dma_buffer(ulong *buf, u32 len)
16{
17 ulong *new_buf;
18
19 if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) {
20 new_buf = (ulong *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN);
21 memcpy(new_buf, buf, len);
22 buf = new_buf;
23 }
24
25 return (ulong)buf;
26}
27
28static int versal_load(xilinx_desc *desc, const void *buf, size_t bsize,
Oleksandr Suvorovc0806cc2022-07-22 17:16:10 +030029 bitstream_type bstype, int flags)
Siva Durga Prasad Paladugub7398972019-08-05 15:54:59 +053030{
31 ulong bin_buf;
32 int ret;
33 u32 buf_lo, buf_hi;
Ibai Erkiaga0768aeb2020-08-04 23:17:26 +010034 u32 ret_payload[PAYLOAD_ARG_CNT];
Siva Durga Prasad Paladugub7398972019-08-05 15:54:59 +053035
36 bin_buf = versal_align_dma_buffer((ulong *)buf, bsize);
37
38 debug("%s called!\n", __func__);
39 flush_dcache_range(bin_buf, bin_buf + bsize);
40
41 buf_lo = lower_32_bits(bin_buf);
42 buf_hi = upper_32_bits(bin_buf);
43
Prasad Kummari48630ae2025-03-27 16:21:59 +053044
45 if (desc->family == xilinx_versal2) {
46 ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_hi,
47 buf_lo, 0, ret_payload);
48 } else {
49 ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
50 buf_hi, 0, ret_payload);
51 }
52
Siva Durga Prasad Paladugub7398972019-08-05 15:54:59 +053053 if (ret)
T Karthik Reddy274410a2020-05-14 07:49:36 -060054 printf("PL FPGA LOAD failed with err: 0x%08x\n", ret);
Siva Durga Prasad Paladugub7398972019-08-05 15:54:59 +053055
56 return ret;
57}
58
59struct xilinx_fpga_op versal_op = {
60 .load = versal_load,
61};