| Philipp Tomsich | d21a4d8 | 2017-06-23 00:12:05 +0200 | [diff] [blame] | 1 | RK3368 dynamic memory controller driver |
| 2 | ======================================= |
| 3 | |
| 4 | The RK3368 DMC (dynamic memory controller) driver supports setup/initialisation |
| 5 | during TPL using configuration data from the DTS (i.e. OF_PLATDATA), based on |
| 6 | the following key configuration data: |
| 7 | (a) a target-frequency (i.e. operating point) for the memory operation |
| 8 | (b) a speed-bin (as defined in JESD-79) for the DDR3 used in hardware |
| 9 | (c) a memory-schedule (i.e. mapping from physical addresses to the address |
| 10 | pins of the memory bus) |
| 11 | |
| 12 | Required properties |
| 13 | ------------------- |
| 14 | |
| 15 | - compatible: "rockchip,rk3368-dmc" |
| 16 | - reg |
| 17 | protocol controller (PCTL) address and PHY controller (DDRPHY) address |
| 18 | - rockchip,ddr-speed-bin |
| 19 | the DDR3 device's speed-bin (as specified according to JESD-79) |
| 20 | DDR3_800D (5-5-5) |
| 21 | DDR3_800E (6-6-6) |
| 22 | DDR3_1066E (6-6-6) |
| 23 | DDR3_1066F (7-7-7) |
| 24 | DDR3_1066G (8-8-8) |
| 25 | DDR3_1333F (7-7-7) |
| 26 | DDR3_1333G (8-8-8) |
| 27 | DDR3_1333H (9-9-9) |
| 28 | DDR3_1333J (10-10-10) |
| 29 | DDR3_1600G (8-8-8) |
| 30 | DDR3_1600H (9-9-9) |
| 31 | DDR3_1600J (10-10-10) |
| 32 | DDR3_1600K (11-11-11) |
| 33 | DDR3_1866J (10-10-10) |
| 34 | DDR3_1866K (11-11-11) |
| 35 | DDR3_1866L (12-12-12) |
| 36 | DDR3_1866M (13-13-13) |
| 37 | DDR3_2133K (11-11-11) |
| 38 | DDR3_2133L (12-12-12) |
| 39 | DDR3_2133M (13-13-13) |
| 40 | DDR3_2133N (14-14-14) |
| 41 | - rockchip,ddr-frequency: |
| 42 | target DDR clock frequency in Hz (not all frequencies may be supported, |
| 43 | as there's some cooperation from the clock-driver required) |
| 44 | - rockchip,memory-schedule: |
| 45 | controls the decoding of physical addresses to DRAM addressing (i.e. how |
| 46 | the physical address maps onto the address pins/chip-select of the device) |
| 47 | DMC_MSCH_CBDR: column -> bank -> device -> row |
| 48 | DMC_MSCH_CBRD: column -> band -> row -> device |
| 49 | DMC_MSCH_CRBD: column -> row -> band -> device |
| 50 | |
| 51 | Example (for DDR3-1600K and 800MHz) |
| 52 | ----------------------------------- |
| 53 | |
| 54 | #include <dt-bindings/memory/rk3368-dmc.h> |
| 55 | |
| 56 | dmc: dmc@ff610000 { |
| Simon Glass | 07a8b62 | 2023-02-13 08:56:35 -0700 | [diff] [blame^] | 57 | bootph-all; |
| Philipp Tomsich | d21a4d8 | 2017-06-23 00:12:05 +0200 | [diff] [blame] | 58 | compatible = "rockchip,rk3368-dmc"; |
| 59 | reg = <0 0xff610000 0 0x400 |
| 60 | 0 0xff620000 0 0x400>; |
| 61 | }; |
| 62 | |
| 63 | &dmc { |
| 64 | rockchip,ddr-speed-bin = <DDR3_1600K>; |
| 65 | rockchip,ddr-frequency = <800000000>; |
| 66 | rockchip,memory-schedule = <DMC_MSCH_CBRD>; |
| 67 | }; |