| wdenk | 452cfd6 | 2002-11-19 11:04:11 +0000 | [diff] [blame] | 1 | |
| 2 | #ifndef _MACROS_H |
| 3 | #define _MACROS_H |
| 4 | |
| 5 | /* |
| 6 | ** Load a long integer into a register |
| 7 | */ |
| wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 8 | .macro liw reg, value |
| 9 | lis \reg, \value@h |
| 10 | ori \reg, \reg, \value@l |
| 11 | .endm |
| wdenk | 452cfd6 | 2002-11-19 11:04:11 +0000 | [diff] [blame] | 12 | |
| 13 | |
| wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 14 | /* |
| wdenk | 452cfd6 | 2002-11-19 11:04:11 +0000 | [diff] [blame] | 15 | ** Generate config_addr request |
| 16 | ** This macro expects the values in registers: |
| 17 | ** r3 - bus |
| 18 | ** r4 - devfn |
| 19 | ** r5 - offset |
| 20 | */ |
| wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 21 | .macro config_addr |
| wdenk | 452cfd6 | 2002-11-19 11:04:11 +0000 | [diff] [blame] | 22 | rlwinm r9, r5, 24, 0, 6 |
| 23 | rlwinm r8, r4, 16, 0, 31 |
| 24 | rlwinm r7, r3, 8, 0, 31 |
| 25 | or r9, r8, r9 |
| 26 | or r9, r7, r9 |
| 27 | ori r9, r9, 0x80 |
| 28 | liw r10, 0xfec00cf8 |
| 29 | stw r9, 0(r10) |
| 30 | eieio |
| 31 | sync |
| 32 | .endm |
| 33 | |
| wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 34 | |
| wdenk | 452cfd6 | 2002-11-19 11:04:11 +0000 | [diff] [blame] | 35 | /* |
| 36 | ** Generate config_data address |
| 37 | */ |
| 38 | .macro config_data mask |
| 39 | andi. r9, r5, \mask |
| 40 | addi r9, r9, 0xcfc |
| 41 | oris r9, r9, 0xfee0 |
| 42 | .endm |
| 43 | |
| 44 | |
| 45 | /* |
| 46 | ** Write a byte value to an output port |
| 47 | */ |
| wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 48 | .macro outb port, value |
| 49 | lis r2, 0xfe00 |
| 50 | li r0, \value |
| 51 | stb r0, \port(r2) |
| 52 | .endm |
| wdenk | 452cfd6 | 2002-11-19 11:04:11 +0000 | [diff] [blame] | 53 | |
| 54 | |
| 55 | /* |
| 56 | ** Write a register byte value to an output port |
| 57 | */ |
| wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 58 | .macro outbr port, value |
| 59 | lis r2, 0xfe00 |
| 60 | stb \value, \port(r2) |
| 61 | .endm |
| wdenk | 452cfd6 | 2002-11-19 11:04:11 +0000 | [diff] [blame] | 62 | |
| 63 | |
| wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 64 | /* |
| wdenk | 452cfd6 | 2002-11-19 11:04:11 +0000 | [diff] [blame] | 65 | ** Read a byte value from a port into a specified register |
| 66 | */ |
| wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 67 | .macro inb reg, port |
| 68 | lis r2, 0xfe00 |
| 69 | lbz \reg, \port(r2) |
| 70 | .endm |
| wdenk | 452cfd6 | 2002-11-19 11:04:11 +0000 | [diff] [blame] | 71 | |
| 72 | |
| 73 | /* |
| 74 | ** Write a byte to the SuperIO config area |
| 75 | */ |
| wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 76 | .macro siowb offset, value |
| 77 | li r3, 0 |
| 78 | li r4, (7<<3) |
| 79 | li r5, \offset |
| 80 | li r6, \value |
| 81 | bl pci_write_cfg_byte |
| 82 | .endm |
| wdenk | 452cfd6 | 2002-11-19 11:04:11 +0000 | [diff] [blame] | 83 | |
| 84 | #endif |