Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 1 | /* |
| 2 | * ti_armv7_common.h |
| 3 | * |
| 4 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 7 | * |
| 8 | * The various ARMv7 SoCs from TI all share a number of IP blocks when |
| 9 | * implementing a given feature. Rather than define these in every |
| 10 | * board or even SoC common file, we define a common file to be re-used |
| 11 | * in all cases. While technically true that some of these details are |
| 12 | * configurable at the board design, they are common throughout SoC |
| 13 | * reference platforms as well as custom designs and become de facto |
| 14 | * standards. |
| 15 | */ |
| 16 | |
| 17 | #ifndef __CONFIG_TI_ARMV7_COMMON_H__ |
| 18 | #define __CONFIG_TI_ARMV7_COMMON_H__ |
| 19 | |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 20 | /* Support both device trees and ATAGs. */ |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 21 | #define CONFIG_CMDLINE_TAG |
| 22 | #define CONFIG_SETUP_MEMORY_TAGS |
| 23 | #define CONFIG_INITRD_TAG |
| 24 | |
| 25 | /* |
| 26 | * Our DDR memory always starts at 0x80000000 and U-Boot shall have |
| 27 | * relocated itself to higher in memory by the time this value is used. |
Tom Rini | 96886f2 | 2014-03-28 15:03:29 -0400 | [diff] [blame] | 28 | * However, set this to a 32MB offset to allow for easier Linux kernel |
| 29 | * booting as the default is often used as the kernel load address. |
| 30 | */ |
| 31 | #define CONFIG_SYS_LOAD_ADDR 0x82000000 |
| 32 | |
| 33 | /* |
| 34 | * We setup defaults based on constraints from the Linux kernel, which should |
| 35 | * also be safe elsewhere. We have the default load at 32MB into DDR (for |
| 36 | * the kernel), FDT above 128MB (the maximum location for the end of the |
| 37 | * kernel), and the ramdisk 512KB above that (allowing for hopefully never |
| 38 | * seen large trees). We say all of this must be within the first 256MB |
| 39 | * as that will normally be within the kernel lowmem and thus visible via |
| 40 | * bootm_size and we only run on platforms with 256MB or more of memory. |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 41 | */ |
Tom Rini | 96886f2 | 2014-03-28 15:03:29 -0400 | [diff] [blame] | 42 | #define DEFAULT_LINUX_BOOT_ENV \ |
| 43 | "loadaddr=0x82000000\0" \ |
| 44 | "kernel_addr_r=0x82000000\0" \ |
| 45 | "fdtaddr=0x88000000\0" \ |
| 46 | "fdt_addr_r=0x88000000\0" \ |
| 47 | "rdaddr=0x88080000\0" \ |
| 48 | "ramdisk_addr_r=0x88080000\0" \ |
Sjoerd Simons | 3a3b3d1 | 2015-08-28 15:01:55 +0200 | [diff] [blame] | 49 | "scriptaddr=0x80000000\0" \ |
| 50 | "pxefile_addr_r=0x80100000\0" \ |
Lokesh Vutla | f01f8b3 | 2016-11-29 11:57:59 +0530 | [diff] [blame] | 51 | "bootm_size=0x10000000\0" \ |
| 52 | "boot_fdt=try\0" |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 53 | |
Lokesh Vutla | c2913ac | 2016-11-29 11:58:00 +0530 | [diff] [blame] | 54 | #define DEFAULT_FIT_TI_ARGS \ |
| 55 | "boot_fit=0\0" \ |
Madan Srinivas | d320ab6 | 2017-07-17 13:01:36 -0500 | [diff] [blame] | 56 | "fit_loadaddr=0x87000000\0" \ |
Andrew F. Davis | b482dac | 2017-04-07 09:55:20 -0500 | [diff] [blame] | 57 | "fit_bootfile=fitImage\0" \ |
Lokesh Vutla | c2913ac | 2016-11-29 11:58:00 +0530 | [diff] [blame] | 58 | "update_to_fit=setenv loadaddr ${fit_loadaddr}; setenv bootfile ${fit_bootfile}\0" \ |
Andrew F. Davis | 2470b6f | 2017-03-10 15:53:54 -0600 | [diff] [blame] | 59 | "loadfit=run args_mmc; bootm ${loadaddr}#${fdtfile};\0" \ |
Lokesh Vutla | c2913ac | 2016-11-29 11:58:00 +0530 | [diff] [blame] | 60 | |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 61 | /* |
Enric Balletbò i Serra | 07322c5 | 2013-12-06 21:30:21 +0100 | [diff] [blame] | 62 | * DDR information. If the CONFIG_NR_DRAM_BANKS is not defined, |
| 63 | * we say (for simplicity) that we have 1 bank, always, even when |
| 64 | * we have more. We always start at 0x80000000, and we place the |
| 65 | * initial stack pointer in our SRAM. Otherwise, we can define |
| 66 | * CONFIG_NR_DRAM_BANKS before including this file. |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 67 | */ |
Enric Balletbò i Serra | 07322c5 | 2013-12-06 21:30:21 +0100 | [diff] [blame] | 68 | #ifndef CONFIG_NR_DRAM_BANKS |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 69 | #define CONFIG_NR_DRAM_BANKS 1 |
Enric Balletbò i Serra | 07322c5 | 2013-12-06 21:30:21 +0100 | [diff] [blame] | 70 | #endif |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 71 | #define CONFIG_SYS_SDRAM_BASE 0x80000000 |
Nishanth Menon | b447151 | 2015-07-22 18:05:45 -0500 | [diff] [blame] | 72 | |
| 73 | #ifndef CONFIG_SYS_INIT_SP_ADDR |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 74 | #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ |
| 75 | GENERATED_GBL_DATA_SIZE) |
Nishanth Menon | b447151 | 2015-07-22 18:05:45 -0500 | [diff] [blame] | 76 | #endif |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 77 | |
| 78 | /* Timer information. */ |
| 79 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 80 | |
Mugunthan V N | 7120284 | 2016-07-18 15:10:59 +0530 | [diff] [blame] | 81 | /* |
| 82 | * Disable DM_* for SPL build and can be re-enabled after adding |
| 83 | * DM support in SPL |
| 84 | */ |
| 85 | #ifdef CONFIG_SPL_BUILD |
| 86 | #undef CONFIG_DM_I2C |
| 87 | #endif |
| 88 | |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 89 | /* I2C IP block */ |
| 90 | #define CONFIG_I2C |
Mugunthan V N | f2cc5c3 | 2016-07-18 15:11:02 +0530 | [diff] [blame] | 91 | #ifndef CONFIG_DM_I2C |
Heiko Schocher | f53f2b8 | 2013-10-22 11:03:18 +0200 | [diff] [blame] | 92 | #define CONFIG_SYS_I2C |
Mugunthan V N | f2cc5c3 | 2016-07-18 15:11:02 +0530 | [diff] [blame] | 93 | #else |
| 94 | /* |
| 95 | * Enable CONFIG_DM_I2C_COMPAT temporarily until all the i2c client |
| 96 | * devices are adopted to DM |
| 97 | */ |
| 98 | #define CONFIG_DM_I2C_COMPAT |
| 99 | #endif |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 100 | |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 101 | /* McSPI IP block */ |
| 102 | #define CONFIG_SPI |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 103 | |
| 104 | /* GPIO block */ |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 105 | |
| 106 | /* |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 107 | * The following are general good-enough settings for U-Boot. We set a |
| 108 | * large malloc pool as we generally have a lot of DDR, and we opt for |
| 109 | * function over binary size in the main portion of U-Boot as this is |
| 110 | * generally easily constrained later if needed. We enable the config |
| 111 | * options that give us information in the environment about what board |
| 112 | * we are on so we do not need to rely on the command prompt. We set a |
| 113 | * console baudrate of 115200 and use the default baud rate table. |
| 114 | */ |
Tom Rini | bc3a557 | 2016-09-19 13:05:34 -0400 | [diff] [blame] | 115 | #define CONFIG_SYS_MALLOC_LEN SZ_32M |
Tom Rini | c5e9636 | 2013-08-20 08:53:49 -0400 | [diff] [blame] | 116 | #define CONFIG_ENV_VARS_UBOOT_CONFIG /* Strongly encouraged */ |
| 117 | #define CONFIG_ENV_OVERWRITE /* Overwrite ethaddr / serial# */ |
| 118 | |
| 119 | /* As stated above, the following choices are optional. */ |
| 120 | #define CONFIG_SYS_LONGHELP |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 121 | #define CONFIG_AUTO_COMPLETE |
| 122 | #define CONFIG_CMDLINE_EDITING |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 123 | |
| 124 | /* We set the max number of command args high to avoid HUSH bugs. */ |
| 125 | #define CONFIG_SYS_MAXARGS 64 |
| 126 | |
| 127 | /* Console I/O Buffer Size */ |
Lokesh Vutla | 79b6801 | 2016-11-25 11:14:26 +0530 | [diff] [blame] | 128 | #define CONFIG_SYS_CBSIZE 1024 |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 129 | /* Boot Argument Buffer Size */ |
| 130 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
| 131 | |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 132 | /* |
| 133 | * When we have SPI, NOR or NAND flash we expect to be making use of |
| 134 | * mtdparts, both for ease of use in U-Boot and for passing information |
| 135 | * on to the Linux kernel. |
| 136 | */ |
Nishanth Menon | b447151 | 2015-07-22 18:05:45 -0500 | [diff] [blame] | 137 | #if defined(CONFIG_SPI_BOOT) || defined(CONFIG_NOR) || defined(CONFIG_NAND) || defined(CONFIG_NAND_DAVINCI) |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 138 | #define CONFIG_MTD_DEVICE /* Required for mtdparts */ |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 139 | #endif |
| 140 | |
Guillaume GARDET | af02aa1 | 2014-11-03 14:26:17 +0100 | [diff] [blame] | 141 | #define CONFIG_SUPPORT_RAW_INITRD |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 142 | |
| 143 | /* |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 144 | * Our platforms make use of SPL to initalize the hardware (primarily |
Andrew F. Davis | e2f61e7 | 2016-08-30 14:06:28 -0500 | [diff] [blame] | 145 | * memory) enough for full U-Boot to be loaded. We make use of the general |
| 146 | * SPL framework found under common/spl/. Given our generally common memory |
| 147 | * map, we set a number of related defaults and sizes here. |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 148 | */ |
Sourav Poddar | 5248bba | 2014-05-19 16:53:37 -0400 | [diff] [blame] | 149 | #if !defined(CONFIG_NOR_BOOT) && \ |
| 150 | !(defined(CONFIG_QSPI_BOOT) && defined(CONFIG_AM43XX)) |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 151 | #define CONFIG_SPL_FRAMEWORK |
Andrew F. Davis | e2f61e7 | 2016-08-30 14:06:28 -0500 | [diff] [blame] | 152 | |
| 153 | /* |
| 154 | * We also support Falcon Mode so that the Linux kernel can be booted |
| 155 | * directly from SPL. This is not currently available on HS devices. |
| 156 | */ |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 157 | |
| 158 | /* |
Tom Rini | be73799 | 2014-07-18 11:51:32 -0400 | [diff] [blame] | 159 | * Place the image at the start of the ROM defined image space (per |
| 160 | * CONFIG_SPL_TEXT_BASE and we limit our size to the ROM-defined |
Tom Rini | cfff4aa | 2016-08-26 13:30:43 -0400 | [diff] [blame] | 161 | * downloaded image area minus 1KiB for scratch space. We initalize DRAM as |
| 162 | * soon as we can so that we can place stack, malloc and BSS there. We load |
| 163 | * U-Boot itself into memory at 0x80800000 for legacy reasons (to not conflict |
| 164 | * with older SPLs). We have our BSS be placed 2MiB after this, to allow for |
| 165 | * the default Linux kernel address of 0x80008000 to work with most sized |
| 166 | * kernels, in the Falcon Mode case. We have the SPL malloc pool at the end |
| 167 | * of the BSS area. We suggest that the stack be placed at 32MiB after the |
| 168 | * start of DRAM to allow room for all of the above (handled in Kconfig). |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 169 | */ |
Tom Rini | e10247f | 2014-04-03 15:17:15 -0400 | [diff] [blame] | 170 | #ifndef CONFIG_SYS_TEXT_BASE |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 171 | #define CONFIG_SYS_TEXT_BASE 0x80800000 |
Tom Rini | e10247f | 2014-04-03 15:17:15 -0400 | [diff] [blame] | 172 | #endif |
| 173 | #ifndef CONFIG_SPL_BSS_START_ADDR |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 174 | #define CONFIG_SPL_BSS_START_ADDR 0x80a00000 |
| 175 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ |
Tom Rini | e10247f | 2014-04-03 15:17:15 -0400 | [diff] [blame] | 176 | #endif |
| 177 | #ifndef CONFIG_SYS_SPL_MALLOC_START |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 178 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ |
| 179 | CONFIG_SPL_BSS_MAX_SIZE) |
Tom Rini | bc3a557 | 2016-09-19 13:05:34 -0400 | [diff] [blame] | 180 | #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_8M |
Tom Rini | e10247f | 2014-04-03 15:17:15 -0400 | [diff] [blame] | 181 | #endif |
Tom Rini | cfff4aa | 2016-08-26 13:30:43 -0400 | [diff] [blame] | 182 | #ifndef CONFIG_SPL_MAX_SIZE |
| 183 | #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ |
| 184 | CONFIG_SPL_TEXT_BASE) |
| 185 | #endif |
| 186 | |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 187 | |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 188 | /* FAT sd card locations. */ |
Paul Kocialkowski | 341e8cd | 2014-11-08 23:14:55 +0100 | [diff] [blame] | 189 | #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 |
Guillaume GARDET | 602a16c | 2014-10-15 17:53:11 +0200 | [diff] [blame] | 190 | #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 191 | |
| 192 | #ifdef CONFIG_SPL_OS_BOOT |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 193 | /* FAT */ |
Guillaume GARDET | 602a16c | 2014-10-15 17:53:11 +0200 | [diff] [blame] | 194 | #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" |
| 195 | #define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 196 | |
| 197 | /* RAW SD card / eMMC */ |
Jean-Jacques Hiblot | a090053 | 2017-05-24 12:08:27 +0200 | [diff] [blame] | 198 | #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1700 /* address 0x2E0000 */ |
| 199 | #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x1500 /* address 0x2A0000 */ |
| 200 | #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x200 /* 256KiB */ |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 201 | #endif |
| 202 | |
Tom Rini | f48e5ee | 2013-08-20 08:53:44 -0400 | [diff] [blame] | 203 | /* General parts of the framework, required. */ |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 204 | |
| 205 | #ifdef CONFIG_NAND |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 206 | #define CONFIG_SPL_NAND_BASE |
| 207 | #define CONFIG_SPL_NAND_DRIVERS |
| 208 | #define CONFIG_SPL_NAND_ECC |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 209 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 210 | #endif |
| 211 | #endif /* !CONFIG_NOR_BOOT */ |
| 212 | |
Cooper Jr., Franklin | 07610ab | 2015-04-21 07:51:04 -0500 | [diff] [blame] | 213 | /* Generic Environment Variables */ |
| 214 | |
| 215 | #ifdef CONFIG_CMD_NET |
| 216 | #define NETARGS \ |
| 217 | "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \ |
| 218 | "::off\0" \ |
| 219 | "nfsopts=nolock\0" \ |
| 220 | "rootpath=/export/rootfs\0" \ |
| 221 | "netloadimage=tftp ${loadaddr} ${bootfile}\0" \ |
| 222 | "netloadfdt=tftp ${fdtaddr} ${fdtfile}\0" \ |
| 223 | "netargs=setenv bootargs console=${console} " \ |
| 224 | "${optargs} " \ |
| 225 | "root=/dev/nfs " \ |
| 226 | "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \ |
| 227 | "ip=dhcp\0" \ |
| 228 | "netboot=echo Booting from network ...; " \ |
| 229 | "setenv autoload no; " \ |
| 230 | "dhcp; " \ |
| 231 | "run netloadimage; " \ |
| 232 | "run netloadfdt; " \ |
| 233 | "run netargs; " \ |
| 234 | "bootz ${loadaddr} - ${fdtaddr}\0" |
Cooper Jr., Franklin | dcee9cf | 2015-06-10 08:54:02 -0500 | [diff] [blame] | 235 | #else |
| 236 | #define NETARGS "" |
Cooper Jr., Franklin | 07610ab | 2015-04-21 07:51:04 -0500 | [diff] [blame] | 237 | #endif |
| 238 | |
Matwey V. Kornilov | 5c15b91 | 2015-10-29 21:54:15 +0300 | [diff] [blame] | 239 | #include <config_distro_defaults.h> |
| 240 | |
Tom Rini | a2f4c91 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 241 | #endif /* __CONFIG_TI_ARMV7_COMMON_H__ */ |