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git01.mediatek.com / filogic / uboot / 073e23e2869a013a4e7dd427f3611997cce53d95 / . / arch / arm / dts / ast2600.dtsi
blob: ac0f08b7ea8892645aac8eb83c0d43e105a4edbf [file] [log] [blame]
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2#include <dt-bindings/interrupt-controller/arm-gic.h>
3#include "skeleton.dtsi"
4
5/ {
6 model = "Aspeed BMC";
7 compatible = "aspeed,ast2600";
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&gic>;
11
12 aliases {
13 i2c0 = &i2c0;
14 i2c1 = &i2c1;
15 i2c2 = &i2c2;
16 i2c3 = &i2c3;
17 i2c4 = &i2c4;
18 i2c5 = &i2c5;
19 i2c6 = &i2c6;
20 i2c7 = &i2c7;
21 i2c8 = &i2c8;
22 i2c9 = &i2c9;
23 i2c10 = &i2c10;
24 i2c11 = &i2c11;
25 i2c12 = &i2c12;
26 i2c13 = &i2c13;
27 i2c14 = &i2c14;
28 i2c15 = &i2c15;
29 serial0 = &uart1;
30 serial1 = &uart2;
31 serial2 = &uart3;
32 serial3 = &uart4;
33 serial4 = &uart5;
34 serial5 = &uart6;
35 serial6 = &uart7;
36 serial7 = &uart8;
37 serial8 = &uart9;
38 serial9 = &uart10;
39 serial10 = &uart11;
40 serial11 = &uart12;
41 serial12 = &uart13;
42 };
43
44 cpus {
45 #address-cells = <1>;
46 #size-cells = <0>;
47 enable-method = "aspeed,ast2600-smp";
48
49 cpu@0 {
50 compatible = "arm,cortex-a7";
51 device_type = "cpu";
52 reg = <0xf00>;
53 };
54
55 cpu@1 {
56 compatible = "arm,cortex-a7";
57 device_type = "cpu";
58 reg = <0xf01>;
59 };
60
61 };
62
63 timer {
64 compatible = "arm,armv7-timer";
65 interrupt-parent = <&gic>;
66 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
67 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
68 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
69 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
70 };
71
72 reserved-memory {
73 #address-cells = <1>;
74 #size-cells = <1>;
75 ranges;
76
77 gfx_memory: framebuffer {
78 size = <0x01000000>;
79 alignment = <0x01000000>;
80 compatible = "shared-dma-pool";
81 reusable;
82 };
83
84 video_memory: video {
85 size = <0x04000000>;
86 alignment = <0x01000000>;
87 compatible = "shared-dma-pool";
88 no-map;
89 };
90 };
91
92 ahb {
93 compatible = "simple-bus";
94 #address-cells = <1>;
95 #size-cells = <1>;
96 device_type = "soc";
97 ranges;
98
99 gic: interrupt-controller@40461000 {
100 compatible = "arm,cortex-a7-gic";
101 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
102 #interrupt-cells = <3>;
103 interrupt-controller;
104 interrupt-parent = <&gic>;
105 reg = <0x40461000 0x1000>,
106 <0x40462000 0x1000>,
107 <0x40464000 0x2000>,
108 <0x40466000 0x2000>;
109 };
110
111 ahbc: ahbc@1e600000 {
112 compatible = "aspeed,aspeed-ahbc";
113 reg = < 0x1e600000 0x100>;
114 };
115
116 fmc: flash-controller@1e620000 {
117 reg = < 0x1e620000 0xc4
118 0x20000000 0x10000000 >;
119 #address-cells = <1>;
120 #size-cells = <0>;
121 compatible = "aspeed,ast2600-fmc";
122 status = "disabled";
123 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
124 clocks = <&scu ASPEED_CLK_AHB>;
125 num-cs = <3>;
126 flash@0 {
127 reg = < 0 >;
128 compatible = "jedec,spi-nor";
129 status = "disabled";
130 };
131 flash@1 {
132 reg = < 1 >;
133 compatible = "jedec,spi-nor";
134 status = "disabled";
135 };
136 flash@2 {
137 reg = < 2 >;
138 compatible = "jedec,spi-nor";
139 status = "disabled";
140 };
141 };
142
143 spi1: flash-controller@1e630000 {
144 reg = < 0x1e630000 0xc4
145 0x30000000 0x08000000 >;
146 #address-cells = <1>;
147 #size-cells = <0>;
148 compatible = "aspeed,ast2600-spi";
149 clocks = <&scu ASPEED_CLK_AHB>;
150 num-cs = <2>;
151 status = "disabled";
152 flash@0 {
153 reg = < 0 >;
154 compatible = "jedec,spi-nor";
155 status = "disabled";
156 };
157 flash@1 {
158 reg = < 1 >;
159 compatible = "jedec,spi-nor";
160 status = "disabled";
161 };
162 };
163
164 spi2: flash-controller@1e631000 {
165 reg = < 0x1e631000 0xc4
166 0x50000000 0x08000000 >;
167 #address-cells = <1>;
168 #size-cells = <0>;
169 compatible = "aspeed,ast2600-spi";
170 clocks = <&scu ASPEED_CLK_AHB>;
171 num-cs = <3>;
172 status = "disabled";
173 flash@0 {
174 reg = < 0 >;
175 compatible = "jedec,spi-nor";
176 status = "disabled";
177 };
178 flash@1 {
179 reg = < 1 >;
180 compatible = "jedec,spi-nor";
181 status = "disabled";
182 };
183 flash@2 {
184 reg = < 2 >;
185 compatible = "jedec,spi-nor";
186 status = "disabled";
187 };
188 };
189
190 edac: sdram@1e6e0000 {
191 compatible = "aspeed,ast2600-sdram-edac";
192 reg = <0x1e6e0000 0x174>;
193 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
194 };
195
196 mdio: ethernet@1e650000 {
197 compatible = "aspeed,aspeed-mdio";
198 reg = <0x1e650000 0x40>;
199 resets = <&rst ASPEED_RESET_MII>;
200 status = "disabled";
201 };
202
203 mac0: ftgmac@1e660000 {
204 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
205 reg = <0x1e660000 0x180>, <0x1e650000 0x4>;
206 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>;
208 status = "disabled";
209 };
210
211 mac1: ftgmac@1e680000 {
212 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
213 reg = <0x1e680000 0x180>, <0x1e650008 0x4>;
214 #address-cells = <1>;
215 #size-cells = <0>;
216 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&scu ASPEED_CLK_GATE_MAC2CLK>;
218 status = "disabled";
219 };
220
221 mac2: ftgmac@1e670000 {
222 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
223 reg = <0x1e670000 0x180>, <0x1e650010 0x4>;
224 #address-cells = <1>;
225 #size-cells = <0>;
226 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&scu ASPEED_CLK_GATE_MAC3CLK>;
228 status = "disabled";
229 };
230
231 mac3: ftgmac@1e690000 {
232 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
233 reg = <0x1e690000 0x180>, <0x1e650018 0x4>;
234 #address-cells = <1>;
235 #size-cells = <0>;
236 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&scu ASPEED_CLK_GATE_MAC4CLK>;
238 status = "disabled";
239 };
240
241 ehci0: usb@1e6a1000 {
242 compatible = "aspeed,aspeed-ehci", "usb-ehci";
243 reg = <0x1e6a1000 0x100>;
244 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&scu ASPEED_CLK_GATE_USBPORT1CLK>;
246 pinctrl-names = "default";
247 pinctrl-0 = <&pinctrl_usb2ah_default>;
248 status = "disabled";
249 };
250
251 ehci1: usb@1e6a3000 {
252 compatible = "aspeed,aspeed-ehci", "usb-ehci";
253 reg = <0x1e6a3000 0x100>;
254 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
255 clocks = <&scu ASPEED_CLK_GATE_USBPORT2CLK>;
256 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_usb2bh_default>;
258 status = "disabled";
259 };
260
261 apb {
262 compatible = "simple-bus";
263 #address-cells = <1>;
264 #size-cells = <1>;
265 ranges;
266
267 syscon: syscon@1e6e2000 {
268 compatible = "aspeed,g6-scu", "syscon", "simple-mfd";
269 reg = <0x1e6e2000 0x1000>;
270 #address-cells = <1>;
271 #size-cells = <1>;
272 #clock-cells = <1>;
273 #reset-cells = <1>;
274 ranges = <0 0x1e6e2000 0x1000>;
275
276 pinctrl: pinctrl {
277 compatible = "aspeed,g6-pinctrl";
278 aspeed,external-nodes = <&gfx &lhc>;
279
280 };
281
282 vga_scratch: scratch {
283 compatible = "aspeed,bmc-misc";
284 };
285
286 scu_ic0: interrupt-controller@0 {
287 #interrupt-cells = <1>;
288 compatible = "aspeed,ast2600-scu-ic";
289 reg = <0x560 0x10>;
290 interrupt-parent = <&gic>;
291 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
292 interrupt-controller;
293 };
294
295 scu_ic1: interrupt-controller@1 {
296 #interrupt-cells = <1>;
297 compatible = "aspeed,ast2600-scu-ic";
298 reg = <0x570 0x10>;
299 interrupt-parent = <&gic>;
300 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
301 interrupt-controller;
302 };
303
304 };
305
306 smp-memram@0 {
307 compatible = "aspeed,ast2600-smpmem", "syscon";
308 reg = <0x1e6e2180 0x40>;
309 };
310
311 gfx: display@1e6e6000 {
312 compatible = "aspeed,ast2500-gfx", "syscon";
313 reg = <0x1e6e6000 0x1000>;
314 reg-io-width = <4>;
315 };
316
317 pcie_bridge0: pcie@1e6ed000 {
318 compatible = "aspeed,ast2600-pcie";
319 #address-cells = <3>;
320 #size-cells = <2>;
321 reg = <0x1e6ed000 0x100>;
322 ranges = <0x81000000 0x0 0x0 0x0 0x0 0x10000>,
323 <0x82000000 0x0 0x60000000 0x60000000 0x0 0x10000000>;
324 device_type = "pci";
325 bus-range = <0x00 0xff>;
326 resets = <&rst ASPEED_RESET_PCIE_DEV_O>;
327 cfg-handle = <&pcie_cfg0>;
328 pinctrl-names = "default";
329 pinctrl-0 = <&pinctrl_pcie0rc_default>;
330
331 status = "disabled";
332 };
333
334 pcie_bridge1: pcie@1e6ed200 {
335 compatible = "aspeed,ast2600-pcie";
336 #address-cells = <3>;
337 #size-cells = <2>;
338 reg = <0x1e6ed200 0x100>;
339 ranges = <0x81000000 0x0 0x0 0x10000 0x00 0x10000>,
340 <0x82000000 0x0 0x70000000 0x70000000 0x0 0x10000000>;
341 device_type = "pci";
342 bus-range = <0x00 0xff>;
343 resets = <&rst ASPEED_RESET_PCIE_RC_O>;
344 cfg-handle = <&pcie_cfg1>;
345 pinctrl-names = "default";
346 pinctrl-0 = <&pinctrl_pcie1rc_default>;
347
348 status = "disabled";
349 };
350
351 sdhci: sdhci@1e740000 {
352 #interrupt-cells = <1>;
353 compatible = "aspeed,aspeed-sdhci-irq", "simple-mfd";
354 reg = <0x1e740000 0x1000>;
355 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
356 interrupt-controller;
357 clocks = <&scu ASPEED_CLK_GATE_SDCLK>,
358 <&scu ASPEED_CLK_GATE_SDEXTCLK>;
359 clock-names = "ctrlclk", "extclk";
360 #address-cells = <1>;
361 #size-cells = <1>;
362 ranges = <0x0 0x1e740000 0x1000>;
363
364 sdhci_slot0: sdhci_slot0@100 {
365 compatible = "aspeed,sdhci-ast2600";
366 reg = <0x100 0x100>;
367 interrupts = <0>;
368 interrupt-parent = <&sdhci>;
369 sdhci,auto-cmd12;
370 clocks = <&scu ASPEED_CLK_SDIO>;
371 status = "disabled";
372 };
373
374 sdhci_slot1: sdhci_slot1@200 {
375 compatible = "aspeed,sdhci-ast2600";
376 reg = <0x200 0x100>;
377 interrupts = <1>;
378 interrupt-parent = <&sdhci>;
379 sdhci,auto-cmd12;
380 clocks = <&scu ASPEED_CLK_SDIO>;
381 status = "disabled";
382 };
383 };
384
385 emmc: emmc@1e750000 {
386 #interrupt-cells = <1>;
387 compatible = "aspeed,aspeed-emmc-irq", "simple-mfd";
388 reg = <0x1e750000 0x1000>;
389 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
390 interrupt-controller;
391 clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>,
392 <&scu ASPEED_CLK_GATE_EMMCEXTCLK>;
393 clock-names = "ctrlclk", "extclk";
394 #address-cells = <1>;
395 #size-cells = <1>;
396 ranges = <0x0 0x1e750000 0x1000>;
397
398 emmc_slot0: emmc_slot0@100 {
399 compatible = "aspeed,emmc-ast2600";
400 reg = <0x100 0x100>;
401 interrupts = <0>;
402 interrupt-parent = <&emmc>;
403 clocks = <&scu ASPEED_CLK_EMMC>;
404 status = "disabled";
405 };
406 };
407
408 h2x: h2x@1e770000 {
409 compatible = "aspeed,ast2600-h2x";
410 reg = <0x1e770000 0x100>;
411 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
412 resets = <&rst ASPEED_RESET_H2X>;
413 #address-cells = <1>;
414 #size-cells = <1>;
415 ranges = <0x0 0x1e770000 0x100>;
416
417 status = "disabled";
418
419 pcie_cfg0: cfg0@80 {
420 reg = <0x80 0x80>;
421 compatible = "aspeed,ast2600-pcie-cfg";
422 };
423
424 pcie_cfg1: cfg1@C0 {
425 compatible = "aspeed,ast2600-pcie-cfg";
426 reg = <0xC0 0x80>;
427 };
428 };
429
430 gpio0: gpio@1e780000 {
431 compatible = "aspeed,ast2600-gpio";
432 reg = <0x1e780000 0x1000>;
433 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
434 #gpio-cells = <2>;
435 gpio-controller;
436 interrupt-controller;
437 gpio-ranges = <&pinctrl 0 0 220>;
438 ngpios = <208>;
439 };
440
441 gpio1: gpio@1e780800 {
442 compatible = "aspeed,ast2600-gpio";
443 reg = <0x1e780800 0x800>;
444 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
445 #gpio-cells = <2>;
446 gpio-controller;
447 interrupt-controller;
448 gpio-ranges = <&pinctrl 0 0 208>;
449 ngpios = <36>;
450 };
451
452 uart1: serial@1e783000 {
453 compatible = "ns16550a";
454 reg = <0x1e783000 0x20>;
455 reg-shift = <2>;
456 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&scu ASPEED_CLK_GATE_UART1CLK>;
458 clock-frequency = <1846154>;
459 no-loopback-test;
460 status = "disabled";
461 };
462
463 uart5: serial@1e784000 {
464 compatible = "ns16550a";
465 reg = <0x1e784000 0x1000>;
466 reg-shift = <2>;
467 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&scu ASPEED_CLK_GATE_UART5CLK>;
469 clock-frequency = <1846154>;
470 no-loopback-test;
471 status = "disabled";
472 };
473
474 wdt1: watchdog@1e785000 {
475 compatible = "aspeed,ast2600-wdt";
476 reg = <0x1e785000 0x40>;
477 };
478
479 wdt2: watchdog@1e785040 {
480 compatible = "aspeed,ast2600-wdt";
481 reg = <0x1e785040 0x40>;
482 };
483
484 wdt3: watchdog@1e785080 {
485 compatible = "aspeed,ast2600-wdt";
486 reg = <0x1e785080 0x40>;
487 };
488
489 wdt4: watchdog@1e7850C0 {
490 compatible = "aspeed,ast2600-wdt";
491 reg = <0x1e7850C0 0x40>;
492 };
493
494 lpc: lpc@1e789000 {
495 compatible = "aspeed,ast2600-lpc", "simple-mfd", "syscon";
496 reg = <0x1e789000 0x1000>;
497
498 #address-cells = <1>;
499 #size-cells = <1>;
500 ranges = <0x0 0x1e789000 0x1000>;
501
502 kcs1: kcs1@0 {
503 compatible = "aspeed,ast2600-kcs-bmc";
504 reg = <0x0 0x80>;
505 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
506 kcs_chan = <1>;
507 kcs_addr = <0xCA0>;
508 status = "disabled";
509 };
510
511 kcs2: kcs2@0 {
512 compatible = "aspeed,ast2600-kcs-bmc";
513 reg = <0x0 0x80>;
514 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
515 kcs_chan = <2>;
516 kcs_addr = <0xCA8>;
517 status = "disabled";
518 };
519
520 kcs3: kcs3@0 {
521 compatible = "aspeed,ast2600-kcs-bmc";
522 reg = <0x0 0x80>;
523 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
524 kcs_chan = <3>;
525 kcs_addr = <0xCA2>;
526 };
527
528 kcs4: kcs4@0 {
529 compatible = "aspeed,ast2600-kcs-bmc";
530 reg = <0x0 0x120>;
531 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
532 kcs_chan = <4>;
533 kcs_addr = <0xCA4>;
534 status = "disabled";
535 };
536
537 lpc_ctrl: lpc-ctrl@80 {
538 compatible = "aspeed,ast2600-lpc-ctrl";
539 reg = <0x80 0x80>;
540 status = "disabled";
541 };
542
543 lpc_snoop: lpc-snoop@80 {
544 compatible = "aspeed,ast2600-lpc-snoop";
545 reg = <0x80 0x80>;
546 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
547 status = "disabled";
548 };
549
550 lhc: lhc@a0 {
551 compatible = "aspeed,ast2600-lhc";
552 reg = <0xa0 0x24 0xc8 0x8>;
553 };
554
555 lpc_reset: reset-controller@98 {
556 compatible = "aspeed,ast2600-lpc-reset";
557 reg = <0x98 0x4>;
558 #reset-cells = <1>;
559 status = "disabled";
560 };
561
562 ibt: ibt@140 {
563 compatible = "aspeed,ast2600-ibt-bmc";
564 reg = <0x140 0x18>;
565 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
566 status = "disabled";
567 };
568
569 sio_regs: regs {
570 compatible = "aspeed,bmc-misc";
571 };
572
573 mbox: mbox@200 {
574 compatible = "aspeed,ast2600-mbox";
575 reg = <0x200 0x5c>;
576 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
577 #mbox-cells = <1>;
578 status = "disabled";
579 };
580 };
581
582 uart2: serial@1e78d000 {
583 compatible = "ns16550a";
584 reg = <0x1e78d000 0x20>;
585 reg-shift = <2>;
586 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
587 clocks = <&scu ASPEED_CLK_GATE_UART2CLK>;
588 clock-frequency = <1846154>;
589 no-loopback-test;
590 status = "disabled";
591 };
592
593 uart3: serial@1e78e000 {
594 compatible = "ns16550a";
595 reg = <0x1e78e000 0x20>;
596 reg-shift = <2>;
597 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
598 clocks = <&scu ASPEED_CLK_GATE_UART3CLK>;
599 clock-frequency = <1846154>;
600 no-loopback-test;
601 status = "disabled";
602 };
603
604 uart4: serial@1e78f000 {
605 compatible = "ns16550a";
606 reg = <0x1e78f000 0x20>;
607 reg-shift = <2>;
608 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
609 clocks = <&scu ASPEED_CLK_GATE_UART4CLK>;
610 clock-frequency = <1846154>;
611 no-loopback-test;
612 status = "disabled";
613 };
614
615 i2c: bus@1e78a000 {
616 compatible = "simple-bus";
617 #address-cells = <1>;
618 #size-cells = <1>;
619 ranges = <0 0x1e78a000 0x1000>;
620 };
621
622 fsim0: fsi@1e79b000 {
623 compatible = "aspeed,ast2600-fsi-master", "fsi-master";
624 reg = <0x1e79b000 0x94>;
625 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
626 pinctrl-names = "default";
627 pinctrl-0 = <&pinctrl_fsi1_default>;
628 clocks = <&scu ASPEED_CLK_GATE_FSICLK>;
629 status = "disabled";
630 };
631
632 fsim1: fsi@1e79b100 {
633 compatible = "aspeed,ast2600-fsi-master", "fsi-master";
634 reg = <0x1e79b100 0x94>;
635 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
636 pinctrl-names = "default";
637 pinctrl-0 = <&pinctrl_fsi2_default>;
638 clocks = <&scu ASPEED_CLK_GATE_FSICLK>;
639 status = "disabled";
640 };
641
642 uart6: serial@1e790000 {
643 compatible = "ns16550a";
644 reg = <0x1e790000 0x20>;
645 reg-shift = <2>;
646 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&scu ASPEED_CLK_GATE_UART6CLK>;
648 clock-frequency = <1846154>;
649 no-loopback-test;
650 status = "disabled";
651 };
652
653 uart7: serial@1e790100 {
654 compatible = "ns16550a";
655 reg = <0x1e790100 0x20>;
656 reg-shift = <2>;
657 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
658 clocks = <&scu ASPEED_CLK_GATE_UART7CLK>;
659 clock-frequency = <1846154>;
660 no-loopback-test;
661 status = "disabled";
662 };
663
664 uart8: serial@1e790200 {
665 compatible = "ns16550a";
666 reg = <0x1e790200 0x20>;
667 reg-shift = <2>;
668 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
669 clocks = <&scu ASPEED_CLK_GATE_UART8CLK>;
670 clock-frequency = <1846154>;
671 no-loopback-test;
672 status = "disabled";
673 };
674
675 uart9: serial@1e790300 {
676 compatible = "ns16550a";
677 reg = <0x1e790300 0x20>;
678 reg-shift = <2>;
679 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
680 clocks = <&scu ASPEED_CLK_GATE_UART9CLK>;
681 clock-frequency = <1846154>;
682 no-loopback-test;
683 status = "disabled";
684 };
685
686 uart10: serial@1e790400 {
687 compatible = "ns16550a";
688 reg = <0x1e790400 0x20>;
689 reg-shift = <2>;
690 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
691 clocks = <&scu ASPEED_CLK_GATE_UART10CLK>;
692 clock-frequency = <1846154>;
693 no-loopback-test;
694 status = "disabled";
695 };
696
697 uart11: serial@1e790500 {
698 compatible = "ns16550a";
699 reg = <0x1e790400 0x20>;
700 reg-shift = <2>;
701 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
702 clocks = <&scu ASPEED_CLK_GATE_UART11CLK>;
703 clock-frequency = <1846154>;
704 no-loopback-test;
705 status = "disabled";
706 };
707
708 uart12: serial@1e790600 {
709 compatible = "ns16550a";
710 reg = <0x1e790600 0x20>;
711 reg-shift = <2>;
712 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&scu ASPEED_CLK_GATE_UART12CLK>;
714 clock-frequency = <1846154>;
715 no-loopback-test;
716 status = "disabled";
717 };
718
719 uart13: serial@1e790700 {
720 compatible = "ns16550a";
721 reg = <0x1e790700 0x20>;
722 reg-shift = <2>;
723 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
724 clocks = <&scu ASPEED_CLK_GATE_UART13CLK>;
725 clock-frequency = <1846154>;
726 no-loopback-test;
727 status = "disabled";
728 };
729
730 display_port: dp@1e6eb000 {
731 compatible = "aspeed,ast2600-displayport";
732 reg = <0x1e6eb000 0x200>;
733 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
734 resets = <&rst ASPEED_RESET_DP> ,<&rst ASPEED_RESET_DP_MCU>;
735 status = "disabled";
736 };
737
738 };
739
740 };
741
742};
743
744&i2c {
745 i2cglobal: i2cg@00 {
746 compatible = "aspeed,ast2600-i2c-global";
747 reg = <0x0 0x40>;
748 resets = <&rst ASPEED_RESET_I2C>;
749#if 0
750 new-mode;
751#endif
752 };
753
754 i2c0: i2c@80 {
755 #address-cells = <1>;
756 #size-cells = <0>;
757 #interrupt-cells = <1>;
758
759 reg = <0x80 0x80 0xC00 0x20>;
760 compatible = "aspeed,ast2600-i2c-bus";
761 bus-frequency = <100000>;
762 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
763 clocks = <&scu ASPEED_CLK_APB2>;
764 status = "disabled";
765 };
766
767 i2c1: i2c@100 {
768 #address-cells = <1>;
769 #size-cells = <0>;
770 #interrupt-cells = <1>;
771
772 reg = <0x100 0x80 0xC20 0x20>;
773 compatible = "aspeed,ast2600-i2c-bus";
774 bus-frequency = <100000>;
775 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
776 clocks = <&scu ASPEED_CLK_APB2>;
777 status = "disabled";
778 };
779
780 i2c2: i2c@180 {
781 #address-cells = <1>;
782 #size-cells = <0>;
783 #interrupt-cells = <1>;
784
785 reg = <0x180 0x80 0xC40 0x20>;
786 compatible = "aspeed,ast2600-i2c-bus";
787 bus-frequency = <100000>;
788 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
789 clocks = <&scu ASPEED_CLK_APB2>;
790 };
791
792 i2c3: i2c@200 {
793 #address-cells = <1>;
794 #size-cells = <0>;
795 #interrupt-cells = <1>;
796
797 reg = <0x200 0x40 0xC60 0x20>;
798 compatible = "aspeed,ast2600-i2c-bus";
799 bus-frequency = <100000>;
800 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
801 clocks = <&scu ASPEED_CLK_APB2>;
802 };
803
804 i2c4: i2c@280 {
805 #address-cells = <1>;
806 #size-cells = <0>;
807 #interrupt-cells = <1>;
808
809 reg = <0x280 0x80 0xC80 0x20>;
810 compatible = "aspeed,ast2600-i2c-bus";
811 bus-frequency = <100000>;
812 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
813 clocks = <&scu ASPEED_CLK_APB2>;
814 };
815
816 i2c5: i2c@300 {
817 #address-cells = <1>;
818 #size-cells = <0>;
819 #interrupt-cells = <1>;
820
821 reg = <0x300 0x40 0xCA0 0x20>;
822 compatible = "aspeed,ast2600-i2c-bus";
823 bus-frequency = <100000>;
824 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
825 clocks = <&scu ASPEED_CLK_APB2>;
826 };
827
828 i2c6: i2c@380 {
829 #address-cells = <1>;
830 #size-cells = <0>;
831 #interrupt-cells = <1>;
832
833 reg = <0x380 0x80 0xCC0 0x20>;
834 compatible = "aspeed,ast2600-i2c-bus";
835 bus-frequency = <100000>;
836 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
837 clocks = <&scu ASPEED_CLK_APB2>;
838 };
839
840 i2c7: i2c@400 {
841 #address-cells = <1>;
842 #size-cells = <0>;
843 #interrupt-cells = <1>;
844
845 reg = <0x400 0x80 0xCE0 0x20>;
846 compatible = "aspeed,ast2600-i2c-bus";
847 bus-frequency = <100000>;
848 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
849 clocks = <&scu ASPEED_CLK_APB2>;
850 };
851
852 i2c8: i2c@480 {
853 #address-cells = <1>;
854 #size-cells = <0>;
855 #interrupt-cells = <1>;
856
857 reg = <0x480 0x80 0xD00 0x20>;
858 compatible = "aspeed,ast2600-i2c-bus";
859 bus-frequency = <100000>;
860 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
861 clocks = <&scu ASPEED_CLK_APB2>;
862 };
863
864 i2c9: i2c@500 {
865 #address-cells = <1>;
866 #size-cells = <0>;
867 #interrupt-cells = <1>;
868
869 reg = <0x500 0x80 0xD20 0x20>;
870 compatible = "aspeed,ast2600-i2c-bus";
871 bus-frequency = <100000>;
872 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
873 clocks = <&scu ASPEED_CLK_APB2>;
874 status = "disabled";
875 };
876
877 i2c10: i2c@580 {
878 #address-cells = <1>;
879 #size-cells = <0>;
880 #interrupt-cells = <1>;
881
882 reg = <0x580 0x80 0xD40 0x20>;
883 compatible = "aspeed,ast2600-i2c-bus";
884 bus-frequency = <100000>;
885 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
886 clocks = <&scu ASPEED_CLK_APB2>;
887 status = "disabled";
888 };
889
890 i2c11: i2c@600 {
891 #address-cells = <1>;
892 #size-cells = <0>;
893 #interrupt-cells = <1>;
894
895 reg = <0x600 0x80 0xD60 0x20>;
896 compatible = "aspeed,ast2600-i2c-bus";
897 bus-frequency = <100000>;
898 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
899 clocks = <&scu ASPEED_CLK_APB2>;
900 status = "disabled";
901 };
902
903 i2c12: i2c@680 {
904 #address-cells = <1>;
905 #size-cells = <0>;
906 #interrupt-cells = <1>;
907
908 reg = <0x680 0x80 0xD80 0x20>;
909 compatible = "aspeed,ast2600-i2c-bus";
910 bus-frequency = <100000>;
911 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
912 clocks = <&scu ASPEED_CLK_APB2>;
913 status = "disabled";
914 };
915
916 i2c13: i2c@700 {
917 #address-cells = <1>;
918 #size-cells = <0>;
919 #interrupt-cells = <1>;
920
921 reg = <0x700 0x80 0xDA0 0x20>;
922 compatible = "aspeed,ast2600-i2c-bus";
923 bus-frequency = <100000>;
924 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
925 clocks = <&scu ASPEED_CLK_APB2>;
926 status = "disabled";
927 };
928
929 i2c14: i2c@780 {
930 #address-cells = <1>;
931 #size-cells = <0>;
932 #interrupt-cells = <1>;
933
934 reg = <0x780 0x80 0xDC0 0x20>;
935 compatible = "aspeed,ast2600-i2c-bus";
936 bus-frequency = <100000>;
937 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
938 clocks = <&scu ASPEED_CLK_APB2>;
939 status = "disabled";
940 };
941
942 i2c15: i2c@800 {
943 #address-cells = <1>;
944 #size-cells = <0>;
945 #interrupt-cells = <1>;
946
947 reg = <0x800 0x80 0xDE0 0x20>;
948 compatible = "aspeed,ast2600-i2c-bus";
949 bus-frequency = <100000>;
950 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
951 clocks = <&scu ASPEED_CLK_APB2>;
952 status = "disabled";
953 };
954
955};
956
957&pinctrl {
958 pinctrl_fmcquad_default: fmcquad_default {
959 function = "FMCQUAD";
960 groups = "FMCQUAD";
961 };
962
963 pinctrl_spi1_default: spi1_default {
964 function = "SPI1";
965 groups = "SPI1";
966 };
967
968 pinctrl_spi1abr_default: spi1abr_default {
969 function = "SPI1ABR";
970 groups = "SPI1ABR";
971 };
972
973 pinctrl_spi1cs1_default: spi1cs1_default {
974 function = "SPI1CS1";
975 groups = "SPI1CS1";
976 };
977
978 pinctrl_spi1wp_default: spi1wp_default {
979 function = "SPI1WP";
980 groups = "SPI1WP";
981 };
982
983 pinctrl_spi1quad_default: spi1quad_default {
984 function = "SPI1QUAD";
985 groups = "SPI1QUAD";
986 };
987
988 pinctrl_spi2_default: spi2_default {
989 function = "SPI2";
990 groups = "SPI2";
991 };
992
993 pinctrl_spi2cs1_default: spi2cs1_default {
994 function = "SPI2CS1";
995 groups = "SPI2CS1";
996 };
997
998 pinctrl_spi2cs2_default: spi2cs2_default {
999 function = "SPI2CS2";
1000 groups = "SPI2CS2";
1001 };
1002
1003 pinctrl_spi2quad_default: spi2quad_default {
1004 function = "SPI2QUAD";
1005 groups = "SPI2QUAD";
1006 };
1007
1008 pinctrl_acpi_default: acpi_default {
1009 function = "ACPI";
1010 groups = "ACPI";
1011 };
1012
1013 pinctrl_adc0_default: adc0_default {
1014 function = "ADC0";
1015 groups = "ADC0";
1016 };
1017
1018 pinctrl_adc1_default: adc1_default {
1019 function = "ADC1";
1020 groups = "ADC1";
1021 };
1022
1023 pinctrl_adc10_default: adc10_default {
1024 function = "ADC10";
1025 groups = "ADC10";
1026 };
1027
1028 pinctrl_adc11_default: adc11_default {
1029 function = "ADC11";
1030 groups = "ADC11";
1031 };
1032
1033 pinctrl_adc12_default: adc12_default {
1034 function = "ADC12";
1035 groups = "ADC12";
1036 };
1037
1038 pinctrl_adc13_default: adc13_default {
1039 function = "ADC13";
1040 groups = "ADC13";
1041 };
1042
1043 pinctrl_adc14_default: adc14_default {
1044 function = "ADC14";
1045 groups = "ADC14";
1046 };
1047
1048 pinctrl_adc15_default: adc15_default {
1049 function = "ADC15";
1050 groups = "ADC15";
1051 };
1052
1053 pinctrl_adc2_default: adc2_default {
1054 function = "ADC2";
1055 groups = "ADC2";
1056 };
1057
1058 pinctrl_adc3_default: adc3_default {
1059 function = "ADC3";
1060 groups = "ADC3";
1061 };
1062
1063 pinctrl_adc4_default: adc4_default {
1064 function = "ADC4";
1065 groups = "ADC4";
1066 };
1067
1068 pinctrl_adc5_default: adc5_default {
1069 function = "ADC5";
1070 groups = "ADC5";
1071 };
1072
1073 pinctrl_adc6_default: adc6_default {
1074 function = "ADC6";
1075 groups = "ADC6";
1076 };
1077
1078 pinctrl_adc7_default: adc7_default {
1079 function = "ADC7";
1080 groups = "ADC7";
1081 };
1082
1083 pinctrl_adc8_default: adc8_default {
1084 function = "ADC8";
1085 groups = "ADC8";
1086 };
1087
1088 pinctrl_adc9_default: adc9_default {
1089 function = "ADC9";
1090 groups = "ADC9";
1091 };
1092
1093 pinctrl_bmcint_default: bmcint_default {
1094 function = "BMCINT";
1095 groups = "BMCINT";
1096 };
1097
1098 pinctrl_ddcclk_default: ddcclk_default {
1099 function = "DDCCLK";
1100 groups = "DDCCLK";
1101 };
1102
1103 pinctrl_ddcdat_default: ddcdat_default {
1104 function = "DDCDAT";
1105 groups = "DDCDAT";
1106 };
1107
1108 pinctrl_espi_default: espi_default {
1109 function = "ESPI";
1110 groups = "ESPI";
1111 };
1112
1113 pinctrl_fsi1_default: fsi1_default {
1114 function = "FSI1";
1115 groups = "FSI1";
1116 };
1117
1118 pinctrl_fsi2_default: fsi2_default {
1119 function = "FSI2";
1120 groups = "FSI2";
1121 };
1122
1123 pinctrl_fwspics1_default: fwspics1_default {
1124 function = "FWSPICS1";
1125 groups = "FWSPICS1";
1126 };
1127
1128 pinctrl_fwspics2_default: fwspics2_default {
1129 function = "FWSPICS2";
1130 groups = "FWSPICS2";
1131 };
1132
1133 pinctrl_gpid0_default: gpid0_default {
1134 function = "GPID0";
1135 groups = "GPID0";
1136 };
1137
1138 pinctrl_gpid2_default: gpid2_default {
1139 function = "GPID2";
1140 groups = "GPID2";
1141 };
1142
1143 pinctrl_gpid4_default: gpid4_default {
1144 function = "GPID4";
1145 groups = "GPID4";
1146 };
1147
1148 pinctrl_gpid6_default: gpid6_default {
1149 function = "GPID6";
1150 groups = "GPID6";
1151 };
1152
1153 pinctrl_gpie0_default: gpie0_default {
1154 function = "GPIE0";
1155 groups = "GPIE0";
1156 };
1157
1158 pinctrl_gpie2_default: gpie2_default {
1159 function = "GPIE2";
1160 groups = "GPIE2";
1161 };
1162
1163 pinctrl_gpie4_default: gpie4_default {
1164 function = "GPIE4";
1165 groups = "GPIE4";
1166 };
1167
1168 pinctrl_gpie6_default: gpie6_default {
1169 function = "GPIE6";
1170 groups = "GPIE6";
1171 };
1172
1173 pinctrl_i2c1_default: i2c1_default {
1174 function = "I2C1";
1175 groups = "I2C1";
1176 };
1177 pinctrl_i2c2_default: i2c2_default {
1178 function = "I2C2";
1179 groups = "I2C2";
1180 };
1181
1182 pinctrl_i2c3_default: i2c3_default {
1183 function = "I2C3";
1184 groups = "I2C3";
1185 };
1186
1187 pinctrl_i2c4_default: i2c4_default {
1188 function = "I2C4";
1189 groups = "I2C4";
1190 };
1191
1192 pinctrl_i2c5_default: i2c5_default {
1193 function = "I2C5";
1194 groups = "I2C5";
1195 };
1196
1197 pinctrl_i2c6_default: i2c6_default {
1198 function = "I2C6";
1199 groups = "I2C6";
1200 };
1201
1202 pinctrl_i2c7_default: i2c7_default {
1203 function = "I2C7";
1204 groups = "I2C7";
1205 };
1206
1207 pinctrl_i2c8_default: i2c8_default {
1208 function = "I2C8";
1209 groups = "I2C8";
1210 };
1211
1212 pinctrl_i2c9_default: i2c9_default {
1213 function = "I2C9";
1214 groups = "I2C9";
1215 };
1216
1217 pinctrl_i2c10_default: i2c10_default {
1218 function = "I2C10";
1219 groups = "I2C10";
1220 };
1221
1222 pinctrl_i2c11_default: i2c11_default {
1223 function = "I2C11";
1224 groups = "I2C11";
1225 };
1226
1227 pinctrl_i2c12_default: i2c12_default {
1228 function = "I2C12";
1229 groups = "I2C12";
1230 };
1231
1232 pinctrl_i2c13_default: i2c13_default {
1233 function = "I2C13";
1234 groups = "I2C13";
1235 };
1236
1237 pinctrl_i2c14_default: i2c14_default {
1238 function = "I2C14";
1239 groups = "I2C14";
1240 };
1241
1242 pinctrl_i2c15_default: i2c15_default {
1243 function = "I2C15";
1244 groups = "I2C15";
1245 };
1246
1247 pinctrl_i2c16_default: i2c16_default {
1248 function = "I2C16";
1249 groups = "I2C16";
1250 };
1251
1252 pinctrl_lad0_default: lad0_default {
1253 function = "LAD0";
1254 groups = "LAD0";
1255 };
1256
1257 pinctrl_lad1_default: lad1_default {
1258 function = "LAD1";
1259 groups = "LAD1";
1260 };
1261
1262 pinctrl_lad2_default: lad2_default {
1263 function = "LAD2";
1264 groups = "LAD2";
1265 };
1266
1267 pinctrl_lad3_default: lad3_default {
1268 function = "LAD3";
1269 groups = "LAD3";
1270 };
1271
1272 pinctrl_lclk_default: lclk_default {
1273 function = "LCLK";
1274 groups = "LCLK";
1275 };
1276
1277 pinctrl_lframe_default: lframe_default {
1278 function = "LFRAME";
1279 groups = "LFRAME";
1280 };
1281
1282 pinctrl_lpchc_default: lpchc_default {
1283 function = "LPCHC";
1284 groups = "LPCHC";
1285 };
1286
1287 pinctrl_lpcpd_default: lpcpd_default {
1288 function = "LPCPD";
1289 groups = "LPCPD";
1290 };
1291
1292 pinctrl_lpcplus_default: lpcplus_default {
1293 function = "LPCPLUS";
1294 groups = "LPCPLUS";
1295 };
1296
1297 pinctrl_lpcpme_default: lpcpme_default {
1298 function = "LPCPME";
1299 groups = "LPCPME";
1300 };
1301
1302 pinctrl_lpcrst_default: lpcrst_default {
1303 function = "LPCRST";
1304 groups = "LPCRST";
1305 };
1306
1307 pinctrl_lpcsmi_default: lpcsmi_default {
1308 function = "LPCSMI";
1309 groups = "LPCSMI";
1310 };
1311
1312 pinctrl_lsirq_default: lsirq_default {
1313 function = "LSIRQ";
1314 groups = "LSIRQ";
1315 };
1316
1317 pinctrl_mac1link_default: mac1link_default {
1318 function = "MAC1LINK";
1319 groups = "MAC1LINK";
1320 };
1321
1322 pinctrl_mac2link_default: mac2link_default {
1323 function = "MAC2LINK";
1324 groups = "MAC2LINK";
1325 };
1326
1327 pinctrl_mac3link_default: mac3link_default {
1328 function = "MAC3LINK";
1329 groups = "MAC3LINK";
1330 };
1331
1332 pinctrl_mac4link_default: mac4link_default {
1333 function = "MAC4LINK";
1334 groups = "MAC4LINK";
1335 };
1336
1337 pinctrl_mdio1_default: mdio1_default {
1338 function = "MDIO1";
1339 groups = "MDIO1";
1340 };
1341
1342 pinctrl_mdio2_default: mdio2_default {
1343 function = "MDIO2";
1344 groups = "MDIO2";
1345 };
1346
1347 pinctrl_mdio3_default: mdio3_default {
1348 function = "MDIO3";
1349 groups = "MDIO3";
1350 };
1351
1352 pinctrl_mdio4_default: mdio4_default {
1353 function = "MDIO4";
1354 groups = "MDIO4";
1355 };
1356
1357 pinctrl_rmii1_default: rmii1_default {
1358 function = "RMII1";
1359 groups = "RMII1";
1360 };
1361
1362 pinctrl_rmii2_default: rmii2_default {
1363 function = "RMII2";
1364 groups = "RMII2";
1365 };
1366
1367 pinctrl_rmii3_default: rmii3_default {
1368 function = "RMII3";
1369 groups = "RMII3";
1370 };
1371
1372 pinctrl_rmii4_default: rmii4_default {
1373 function = "RMII4";
1374 groups = "RMII4";
1375 };
1376
1377 pinctrl_rmii1rclk_default: rmii1rclk_default {
1378 function = "RMII1RCLK";
1379 groups = "RMII1RCLK";
1380 };
1381
1382 pinctrl_rmii2rclk_default: rmii2rclk_default {
1383 function = "RMII2RCLK";
1384 groups = "RMII2RCLK";
1385 };
1386
1387 pinctrl_rmii3rclk_default: rmii3rclk_default {
1388 function = "RMII3RCLK";
1389 groups = "RMII3RCLK";
1390 };
1391
1392 pinctrl_rmii4rclk_default: rmii4rclk_default {
1393 function = "RMII4RCLK";
1394 groups = "RMII4RCLK";
1395 };
1396
1397 pinctrl_ncts1_default: ncts1_default {
1398 function = "NCTS1";
1399 groups = "NCTS1";
1400 };
1401
1402 pinctrl_ncts2_default: ncts2_default {
1403 function = "NCTS2";
1404 groups = "NCTS2";
1405 };
1406
1407 pinctrl_ncts3_default: ncts3_default {
1408 function = "NCTS3";
1409 groups = "NCTS3";
1410 };
1411
1412 pinctrl_ncts4_default: ncts4_default {
1413 function = "NCTS4";
1414 groups = "NCTS4";
1415 };
1416
1417 pinctrl_ndcd1_default: ndcd1_default {
1418 function = "NDCD1";
1419 groups = "NDCD1";
1420 };
1421
1422 pinctrl_ndcd2_default: ndcd2_default {
1423 function = "NDCD2";
1424 groups = "NDCD2";
1425 };
1426
1427 pinctrl_ndcd3_default: ndcd3_default {
1428 function = "NDCD3";
1429 groups = "NDCD3";
1430 };
1431
1432 pinctrl_ndcd4_default: ndcd4_default {
1433 function = "NDCD4";
1434 groups = "NDCD4";
1435 };
1436
1437 pinctrl_ndsr1_default: ndsr1_default {
1438 function = "NDSR1";
1439 groups = "NDSR1";
1440 };
1441
1442 pinctrl_ndsr2_default: ndsr2_default {
1443 function = "NDSR2";
1444 groups = "NDSR2";
1445 };
1446
1447 pinctrl_ndsr3_default: ndsr3_default {
1448 function = "NDSR3";
1449 groups = "NDSR3";
1450 };
1451
1452 pinctrl_ndsr4_default: ndsr4_default {
1453 function = "NDSR4";
1454 groups = "NDSR4";
1455 };
1456
1457 pinctrl_ndtr1_default: ndtr1_default {
1458 function = "NDTR1";
1459 groups = "NDTR1";
1460 };
1461
1462 pinctrl_ndtr2_default: ndtr2_default {
1463 function = "NDTR2";
1464 groups = "NDTR2";
1465 };
1466
1467 pinctrl_ndtr3_default: ndtr3_default {
1468 function = "NDTR3";
1469 groups = "NDTR3";
1470 };
1471
1472 pinctrl_ndtr4_default: ndtr4_default {
1473 function = "NDTR4";
1474 groups = "NDTR4";
1475 };
1476
1477 pinctrl_nri1_default: nri1_default {
1478 function = "NRI1";
1479 groups = "NRI1";
1480 };
1481
1482 pinctrl_nri2_default: nri2_default {
1483 function = "NRI2";
1484 groups = "NRI2";
1485 };
1486
1487 pinctrl_nri3_default: nri3_default {
1488 function = "NRI3";
1489 groups = "NRI3";
1490 };
1491
1492 pinctrl_nri4_default: nri4_default {
1493 function = "NRI4";
1494 groups = "NRI4";
1495 };
1496
1497 pinctrl_nrts1_default: nrts1_default {
1498 function = "NRTS1";
1499 groups = "NRTS1";
1500 };
1501
1502 pinctrl_nrts2_default: nrts2_default {
1503 function = "NRTS2";
1504 groups = "NRTS2";
1505 };
1506
1507 pinctrl_nrts3_default: nrts3_default {
1508 function = "NRTS3";
1509 groups = "NRTS3";
1510 };
1511
1512 pinctrl_nrts4_default: nrts4_default {
1513 function = "NRTS4";
1514 groups = "NRTS4";
1515 };
1516
1517 pinctrl_oscclk_default: oscclk_default {
1518 function = "OSCCLK";
1519 groups = "OSCCLK";
1520 };
1521
1522 pinctrl_pewake_default: pewake_default {
1523 function = "PEWAKE";
1524 groups = "PEWAKE";
1525 };
1526
1527 pinctrl_pnor_default: pnor_default {
1528 function = "PNOR";
1529 groups = "PNOR";
1530 };
1531
1532 pinctrl_pwm0_default: pwm0_default {
1533 function = "PWM0";
1534 groups = "PWM0";
1535 };
1536
1537 pinctrl_pwm1_default: pwm1_default {
1538 function = "PWM1";
1539 groups = "PWM1";
1540 };
1541
1542 pinctrl_pwm2_default: pwm2_default {
1543 function = "PWM2";
1544 groups = "PWM2";
1545 };
1546
1547 pinctrl_pwm3_default: pwm3_default {
1548 function = "PWM3";
1549 groups = "PWM3";
1550 };
1551
1552 pinctrl_pwm4_default: pwm4_default {
1553 function = "PWM4";
1554 groups = "PWM4";
1555 };
1556
1557 pinctrl_pwm5_default: pwm5_default {
1558 function = "PWM5";
1559 groups = "PWM5";
1560 };
1561
1562 pinctrl_pwm6_default: pwm6_default {
1563 function = "PWM6";
1564 groups = "PWM6";
1565 };
1566
1567 pinctrl_pwm7_default: pwm7_default {
1568 function = "PWM7";
1569 groups = "PWM7";
1570 };
1571
1572 pinctrl_rgmii1_default: rgmii1_default {
1573 function = "RGMII1";
1574 groups = "RGMII1";
1575 };
1576
1577 pinctrl_rgmii2_default: rgmii2_default {
1578 function = "RGMII2";
1579 groups = "RGMII2";
1580 };
1581
1582 pinctrl_rgmii3_default: rgmii3_default {
1583 function = "RGMII3";
1584 groups = "RGMII3";
1585 };
1586
1587 pinctrl_rgmii4_default: rgmii4_default {
1588 function = "RGMII4";
1589 groups = "RGMII4";
1590 };
1591
1592 pinctrl_rmii1_default: rmii1_default {
1593 function = "RMII1";
1594 groups = "RMII1";
1595 };
1596
1597 pinctrl_rmii2_default: rmii2_default {
1598 function = "RMII2";
1599 groups = "RMII2";
1600 };
1601
1602 pinctrl_rxd1_default: rxd1_default {
1603 function = "RXD1";
1604 groups = "RXD1";
1605 };
1606
1607 pinctrl_rxd2_default: rxd2_default {
1608 function = "RXD2";
1609 groups = "RXD2";
1610 };
1611
1612 pinctrl_rxd3_default: rxd3_default {
1613 function = "RXD3";
1614 groups = "RXD3";
1615 };
1616
1617 pinctrl_rxd4_default: rxd4_default {
1618 function = "RXD4";
1619 groups = "RXD4";
1620 };
1621
1622 pinctrl_salt1_default: salt1_default {
1623 function = "SALT1";
1624 groups = "SALT1";
1625 };
1626
1627 pinctrl_salt10_default: salt10_default {
1628 function = "SALT10";
1629 groups = "SALT10";
1630 };
1631
1632 pinctrl_salt11_default: salt11_default {
1633 function = "SALT11";
1634 groups = "SALT11";
1635 };
1636
1637 pinctrl_salt12_default: salt12_default {
1638 function = "SALT12";
1639 groups = "SALT12";
1640 };
1641
1642 pinctrl_salt13_default: salt13_default {
1643 function = "SALT13";
1644 groups = "SALT13";
1645 };
1646
1647 pinctrl_salt14_default: salt14_default {
1648 function = "SALT14";
1649 groups = "SALT14";
1650 };
1651
1652 pinctrl_salt2_default: salt2_default {
1653 function = "SALT2";
1654 groups = "SALT2";
1655 };
1656
1657 pinctrl_salt3_default: salt3_default {
1658 function = "SALT3";
1659 groups = "SALT3";
1660 };
1661
1662 pinctrl_salt4_default: salt4_default {
1663 function = "SALT4";
1664 groups = "SALT4";
1665 };
1666
1667 pinctrl_salt5_default: salt5_default {
1668 function = "SALT5";
1669 groups = "SALT5";
1670 };
1671
1672 pinctrl_salt6_default: salt6_default {
1673 function = "SALT6";
1674 groups = "SALT6";
1675 };
1676
1677 pinctrl_salt7_default: salt7_default {
1678 function = "SALT7";
1679 groups = "SALT7";
1680 };
1681
1682 pinctrl_salt8_default: salt8_default {
1683 function = "SALT8";
1684 groups = "SALT8";
1685 };
1686
1687 pinctrl_salt9_default: salt9_default {
1688 function = "SALT9";
1689 groups = "SALT9";
1690 };
1691
1692 pinctrl_scl1_default: scl1_default {
1693 function = "SCL1";
1694 groups = "SCL1";
1695 };
1696
1697 pinctrl_scl2_default: scl2_default {
1698 function = "SCL2";
1699 groups = "SCL2";
1700 };
1701
1702 pinctrl_sd1_default: sd1_default {
1703 function = "SD1";
1704 groups = "SD1";
1705 };
1706
1707 pinctrl_sd2_default: sd2_default {
1708 function = "SD2";
1709 groups = "SD2";
1710 };
1711
1712 pinctrl_emmc_default: emmc_default {
1713 function = "EMMC";
1714 groups = "EMMC";
1715 };
1716
1717 pinctrl_emmcg8_default: emmcg8_default {
1718 function = "EMMCG8";
1719 groups = "EMMCG8";
1720 };
1721
1722 pinctrl_sda1_default: sda1_default {
1723 function = "SDA1";
1724 groups = "SDA1";
1725 };
1726
1727 pinctrl_sda2_default: sda2_default {
1728 function = "SDA2";
1729 groups = "SDA2";
1730 };
1731
1732 pinctrl_sgps1_default: sgps1_default {
1733 function = "SGPS1";
1734 groups = "SGPS1";
1735 };
1736
1737 pinctrl_sgps2_default: sgps2_default {
1738 function = "SGPS2";
1739 groups = "SGPS2";
1740 };
1741
1742 pinctrl_sioonctrl_default: sioonctrl_default {
1743 function = "SIOONCTRL";
1744 groups = "SIOONCTRL";
1745 };
1746
1747 pinctrl_siopbi_default: siopbi_default {
1748 function = "SIOPBI";
1749 groups = "SIOPBI";
1750 };
1751
1752 pinctrl_siopbo_default: siopbo_default {
1753 function = "SIOPBO";
1754 groups = "SIOPBO";
1755 };
1756
1757 pinctrl_siopwreq_default: siopwreq_default {
1758 function = "SIOPWREQ";
1759 groups = "SIOPWREQ";
1760 };
1761
1762 pinctrl_siopwrgd_default: siopwrgd_default {
1763 function = "SIOPWRGD";
1764 groups = "SIOPWRGD";
1765 };
1766
1767 pinctrl_sios3_default: sios3_default {
1768 function = "SIOS3";
1769 groups = "SIOS3";
1770 };
1771
1772 pinctrl_sios5_default: sios5_default {
1773 function = "SIOS5";
1774 groups = "SIOS5";
1775 };
1776
1777 pinctrl_siosci_default: siosci_default {
1778 function = "SIOSCI";
1779 groups = "SIOSCI";
1780 };
1781
1782 pinctrl_spi1_default: spi1_default {
1783 function = "SPI1";
1784 groups = "SPI1";
1785 };
1786
1787 pinctrl_spi1cs1_default: spi1cs1_default {
1788 function = "SPI1CS1";
1789 groups = "SPI1CS1";
1790 };
1791
1792 pinctrl_spi1debug_default: spi1debug_default {
1793 function = "SPI1DEBUG";
1794 groups = "SPI1DEBUG";
1795 };
1796
1797 pinctrl_spi1passthru_default: spi1passthru_default {
1798 function = "SPI1PASSTHRU";
1799 groups = "SPI1PASSTHRU";
1800 };
1801
1802 pinctrl_spi2ck_default: spi2ck_default {
1803 function = "SPI2CK";
1804 groups = "SPI2CK";
1805 };
1806
1807 pinctrl_spi2cs0_default: spi2cs0_default {
1808 function = "SPI2CS0";
1809 groups = "SPI2CS0";
1810 };
1811
1812 pinctrl_spi2cs1_default: spi2cs1_default {
1813 function = "SPI2CS1";
1814 groups = "SPI2CS1";
1815 };
1816
1817 pinctrl_spi2miso_default: spi2miso_default {
1818 function = "SPI2MISO";
1819 groups = "SPI2MISO";
1820 };
1821
1822 pinctrl_spi2mosi_default: spi2mosi_default {
1823 function = "SPI2MOSI";
1824 groups = "SPI2MOSI";
1825 };
1826
1827 pinctrl_timer3_default: timer3_default {
1828 function = "TIMER3";
1829 groups = "TIMER3";
1830 };
1831
1832 pinctrl_timer4_default: timer4_default {
1833 function = "TIMER4";
1834 groups = "TIMER4";
1835 };
1836
1837 pinctrl_timer5_default: timer5_default {
1838 function = "TIMER5";
1839 groups = "TIMER5";
1840 };
1841
1842 pinctrl_timer6_default: timer6_default {
1843 function = "TIMER6";
1844 groups = "TIMER6";
1845 };
1846
1847 pinctrl_timer7_default: timer7_default {
1848 function = "TIMER7";
1849 groups = "TIMER7";
1850 };
1851
1852 pinctrl_timer8_default: timer8_default {
1853 function = "TIMER8";
1854 groups = "TIMER8";
1855 };
1856
1857 pinctrl_txd1_default: txd1_default {
1858 function = "TXD1";
1859 groups = "TXD1";
1860 };
1861
1862 pinctrl_txd2_default: txd2_default {
1863 function = "TXD2";
1864 groups = "TXD2";
1865 };
1866
1867 pinctrl_txd3_default: txd3_default {
1868 function = "TXD3";
1869 groups = "TXD3";
1870 };
1871
1872 pinctrl_txd4_default: txd4_default {
1873 function = "TXD4";
1874 groups = "TXD4";
1875 };
1876
1877 pinctrl_uart6_default: uart6_default {
1878 function = "UART6";
1879 groups = "UART6";
1880 };
1881
1882 pinctrl_usbcki_default: usbcki_default {
1883 function = "USBCKI";
1884 groups = "USBCKI";
1885 };
1886
1887 pinctrl_usb2ah_default: usb2ah_default {
1888 function = "USB2AH";
1889 groups = "USB2AH";
1890 };
1891
1892 pinctrl_usb11bhid_default: usb11bhid_default {
1893 function = "USB11BHID";
1894 groups = "USB11BHID";
1895 };
1896
1897 pinctrl_usb2bh_default: usb2bh_default {
1898 function = "USB2BH";
1899 groups = "USB2BH";
1900 };
1901
1902 pinctrl_vgabiosrom_default: vgabiosrom_default {
1903 function = "VGABIOSROM";
1904 groups = "VGABIOSROM";
1905 };
1906
1907 pinctrl_vgahs_default: vgahs_default {
1908 function = "VGAHS";
1909 groups = "VGAHS";
1910 };
1911
1912 pinctrl_vgavs_default: vgavs_default {
1913 function = "VGAVS";
1914 groups = "VGAVS";
1915 };
1916
1917 pinctrl_vpi24_default: vpi24_default {
1918 function = "VPI24";
1919 groups = "VPI24";
1920 };
1921
1922 pinctrl_vpo_default: vpo_default {
1923 function = "VPO";
1924 groups = "VPO";
1925 };
1926
1927 pinctrl_wdtrst1_default: wdtrst1_default {
1928 function = "WDTRST1";
1929 groups = "WDTRST1";
1930 };
1931
1932 pinctrl_wdtrst2_default: wdtrst2_default {
1933 function = "WDTRST2";
1934 groups = "WDTRST2";
1935 };
1936
1937 pinctrl_pcie0rc_default: pcie0rc_default {
1938 function = "PCIE0RC";
1939 groups = "PCIE0RC";
1940 };
1941
1942 pinctrl_pcie1rc_default: pcie1rc_default {
1943 function = "PCIE1RC";
1944 groups = "PCIE1RC";
1945 };
1946};