blob: a7fb92e62a9733ae4b5a81e5b4eec568d38bc2ce [file] [log] [blame]
Mike Frysingercc244082008-10-12 21:25:33 -04001/*
2 * U-boot - Configuration file for BF538F EZ-Kit Lite board
3 */
4
5#ifndef __CONFIG_BF538F_EZKIT_H__
6#define __CONFIG_BF538F_EZKIT_H__
7
8#include <asm/blackfin-config-pre.h>
9
10
11/*
12 * Processor Settings
13 */
14#define CONFIG_BFIN_CPU bf538-0.4
15#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
16
17
18/*
19 * Clock Settings
20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
22 */
23/* CONFIG_CLKIN_HZ is any value in Hz */
24#define CONFIG_CLKIN_HZ 25000000
25/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
26/* 1 = CLKIN / 2 */
27#define CONFIG_CLKIN_HALF 0
28/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
29/* 1 = bypass PLL */
30#define CONFIG_PLL_BYPASS 0
31/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
32/* Values can range from 0-63 (where 0 means 64) */
33#define CONFIG_VCO_MULT 21
34/* CCLK_DIV controls the core clock divider */
35/* Values can be 1, 2, 4, or 8 ONLY */
36#define CONFIG_CCLK_DIV 1
37/* SCLK_DIV controls the system clock divider */
38/* Values can range from 1-15 */
39#define CONFIG_SCLK_DIV 4
40
41
42/*
43 * Memory Settings
44 */
45#define CONFIG_MEM_ADD_WDTH 10
46#define CONFIG_MEM_SIZE 64
47
48#define CONFIG_EBIU_SDRRC_VAL (0x03F6)
49#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | PSS | TWR_2 | TRCD_3 | TRP_3 | TRAS_6 | PASR_ALL | CL_3)
50
51#define CONFIG_EBIU_AMGCTL_VAL (CDPRIO | AMBEN_ALL | AMCKEN)
52#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
53#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
54
55#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
56#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
57
58
59/*
60 * Network Settings
61 */
62#define ADI_CMDS_NETWORK 1
63#define CONFIG_DRIVER_SMC91111 1
64#define CONFIG_SMC91111_BASE 0x20310300
65#define CONFIG_HOSTNAME bf538f-ezkit
66/* Uncomment next line to use fixed MAC address */
67/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
68
69
70/*
71 * Flash Settings
72 */
73#define CONFIG_FLASH_CFI_DRIVER
74#define CONFIG_SYS_FLASH_BASE 0x20000000
75#define CONFIG_SYS_FLASH_CFI
76#define CONFIG_SYS_FLASH_PROTECTION
77#define CONFIG_SYS_MAX_FLASH_BANKS 1
78#define CONFIG_SYS_MAX_FLASH_SECT 71
79
80
81/*
82 * SPI Settings
83 */
84#define CONFIG_BFIN_SPI
85#define CONFIG_ENV_SPI_MAX_HZ 30000000
86#define CONFIG_SF_DEFAULT_HZ 30000000
87#define CONFIG_SPI_FLASH
88#define CONFIG_SPI_FLASH_ATMEL
89#define CONFIG_SPI_FLASH_SPANSION
90#define CONFIG_SPI_FLASH_STMICRO
91#define CONFIG_SPI_FLASH_WINBOND
92
93
94/*
95 * Env Storage Settings
96 */
97#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
98#define CONFIG_ENV_IS_IN_SPI_FLASH
99#define CONFIG_ENV_OFFSET 0x4000
100#define CONFIG_ENV_SIZE 0x2000
101#define CONFIG_ENV_SECT_SIZE 0x2000
102#else
103#define CONFIG_ENV_IS_IN_FLASH
104#define CONFIG_ENV_OFFSET 0x4000
105#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
106#define CONFIG_ENV_SIZE 0x2000
107#define CONFIG_ENV_SECT_SIZE 0x2000
108#endif
109#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
110#define ENV_IS_EMBEDDED
111#else
112#define ENV_IS_EMBEDDED_CUSTOM
113#endif
114
115
116/*
117 * I2C Settings
118 */
119#define CONFIG_BFIN_TWI_I2C 1
120#define CONFIG_HARD_I2C 1
121#define CONFIG_SYS_I2C_SPEED 50000
122#define CONFIG_SYS_I2C_SLAVE 0
123
124
125/*
126 * Misc Settings
127 */
128#define CONFIG_RTC_BFIN
129#define CONFIG_UART_CONSOLE 0
130
131
132/*
133 * Pull in common ADI header for remaining command/environment setup
134 */
135#include <configs/bfin_adi_common.h>
136
137#include <asm/blackfin-config-post.h>
138
139#endif