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Marcel Ziswiler99d768b2019-05-31 18:56:39 +03001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 Toradex
4 */
5
6#include <common.h>
Simon Glassafb02152019-12-28 10:45:01 -07007#include <cpu_func.h>
Simon Glassa7b51302019-11-14 12:57:46 -07008#include <init.h>
Simon Glass3ba929a2020-10-30 21:38:53 -06009#include <asm/global_data.h>
Marcel Ziswiler99d768b2019-05-31 18:56:39 +030010
11#include <asm/arch/clock.h>
12#include <asm/arch/imx8-pins.h>
13#include <asm/arch/iomux.h>
Peng Fan2e0644a2023-04-28 12:08:09 +080014#include <firmware/imx/sci/sci.h>
Marcel Ziswiler99d768b2019-05-31 18:56:39 +030015#include <asm/arch/sys_proto.h>
16#include <asm/gpio.h>
17#include <asm/io.h>
Simon Glass5e6201b2019-08-01 09:46:51 -060018#include <env.h>
Marcel Ziswiler99d768b2019-05-31 18:56:39 +030019#include <errno.h>
20#include <linux/libfdt.h>
21
22#include "../common/tdx-cfg-block.h"
23
24DECLARE_GLOBAL_DATA_PTR;
25
26#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
27 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
28 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
29 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
30
31static iomux_cfg_t uart3_pads[] = {
32 SC_P_FLEXCAN2_RX | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL),
33 SC_P_FLEXCAN2_TX | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL),
34 /* Transceiver FORCEOFF# signal, mux to use pull-up */
35 SC_P_QSPI0B_DQS | MUX_MODE_ALT(4) | MUX_PAD_CTRL(UART_PAD_CTRL),
36};
37
38static void setup_iomux_uart(void)
39{
40 imx8_iomux_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
41}
42
Max Krummenacher88c70712023-03-03 14:26:32 +010043static int is_imx8dx(void)
Igor Opaniukdcc63c12020-10-22 11:21:43 +030044{
Max Krummenacher88c70712023-03-03 14:26:32 +010045 u32 val = 0;
Peng Fanbffd4dc2023-06-15 18:09:00 +080046 int sc_err = sc_misc_otp_fuse_read(-1, 6, &val);
Igor Opaniukdcc63c12020-10-22 11:21:43 +030047
Peng Fanbffd4dc2023-06-15 18:09:00 +080048 if (sc_err) {
Igor Opaniukdcc63c12020-10-22 11:21:43 +030049 /* DX has two A35 cores disabled */
Max Krummenacher88c70712023-03-03 14:26:32 +010050 return (val & 0xf) != 0x0;
Igor Opaniukdcc63c12020-10-22 11:21:43 +030051 }
Max Krummenacher88c70712023-03-03 14:26:32 +010052 return false;
53}
Igor Opaniukdcc63c12020-10-22 11:21:43 +030054
Max Krummenacher88c70712023-03-03 14:26:32 +010055void board_mem_get_layout(u64 *phys_sdram_1_start,
56 u64 *phys_sdram_1_size,
57 u64 *phys_sdram_2_start,
58 u64 *phys_sdram_2_size)
59{
Igor Opaniukdcc63c12020-10-22 11:21:43 +030060 *phys_sdram_1_start = PHYS_SDRAM_1;
Max Krummenacher88c70712023-03-03 14:26:32 +010061 if (is_imx8dx())
Igor Opaniukdcc63c12020-10-22 11:21:43 +030062 /* Our DX based SKUs only have 1 GB RAM */
63 *phys_sdram_1_size = SZ_1G;
64 else
65 *phys_sdram_1_size = PHYS_SDRAM_1_SIZE;
66 *phys_sdram_2_start = PHYS_SDRAM_2;
67 *phys_sdram_2_size = PHYS_SDRAM_2_SIZE;
68}
69
Marcel Ziswiler99d768b2019-05-31 18:56:39 +030070int board_early_init_f(void)
71{
72 sc_pm_clock_rate_t rate;
Peng Fanbffd4dc2023-06-15 18:09:00 +080073 int err;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +030074
75 /*
76 * This works around that having only UART3 up the baudrate is 1.2M
77 * instead of 115.2k. Set UART0 clock root to 80 MHz
78 */
79 rate = 80000000;
80 err = sc_pm_set_clock_rate(-1, SC_R_UART_0, SC_PM_CLK_PER, &rate);
Peng Fanbffd4dc2023-06-15 18:09:00 +080081 if (err)
Marcel Ziswiler99d768b2019-05-31 18:56:39 +030082 return 0;
83
Anatolij Gustschinef156d22019-06-12 13:35:25 +020084 /* Set UART3 clock root to 80 MHz and enable it */
85 rate = SC_80MHZ;
86 err = sc_pm_setup_uart(SC_R_UART_3, rate);
Peng Fanbffd4dc2023-06-15 18:09:00 +080087 if (err)
Marcel Ziswiler99d768b2019-05-31 18:56:39 +030088 return 0;
89
90 setup_iomux_uart();
91
92 return 0;
93}
94
95#if IS_ENABLED(CONFIG_DM_GPIO)
96static void board_gpio_init(void)
97{
98 /* TODO */
99}
100#else
101static inline void board_gpio_init(void) {}
102#endif
103
104#if IS_ENABLED(CONFIG_FEC_MXC)
105#include <miiphy.h>
106
107int board_phy_config(struct phy_device *phydev)
108{
109 if (phydev->drv->config)
110 phydev->drv->config(phydev);
111
112 return 0;
113}
114#endif
115
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300116int checkboard(void)
117{
118 puts("Model: Toradex Colibri iMX8X\n");
119
120 build_info();
121 print_bootinfo();
122
123 return 0;
124}
125
Andrejs Cainikovsa4d81542023-03-03 14:26:33 +0100126static void select_dt_from_module_version(void)
127{
128 /*
129 * The dtb filename is constructed from ${soc}-colibri-${fdt_board}.dtb.
130 * Set soc depending on the used SoC.
131 */
132 if (is_imx8dx())
133 env_set("soc", "imx8dx");
134 else
135 env_set("soc", "imx8qxp");
136}
137
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300138int board_init(void)
139{
140 board_gpio_init();
141
142 return 0;
143}
144
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300145/*
146 * Board specific reset that is system reset.
147 */
Harald Seiler6f14d5f2020-12-15 16:47:52 +0100148void reset_cpu(void)
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300149{
150 /* TODO */
151}
152
153#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900154int ft_board_setup(void *blob, struct bd_info *bd)
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300155{
156 return ft_common_board_setup(blob, bd);
157}
158#endif
159
160int board_mmc_get_env_dev(int devno)
161{
162 return devno;
163}
164
165int board_late_init(void)
166{
167#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
168/* TODO move to common */
169 env_set("board_name", "Colibri iMX8QXP");
170 env_set("board_rev", "v1.0");
171#endif
172
Andrejs Cainikovsaa390ed2023-04-03 13:14:25 +0200173 build_info();
174
Andrejs Cainikovsa4d81542023-03-03 14:26:33 +0100175 select_dt_from_module_version();
176
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300177 return 0;
178}