| Tero Kristo | bf4f597 | 2020-06-16 11:03:09 +0300 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* |
| 3 | * Copyright 2017 Texas Instruments, Inc. |
| 4 | */ |
| 5 | #ifndef __DT_BINDINGS_CLK_OMAP5_H |
| 6 | #define __DT_BINDINGS_CLK_OMAP5_H |
| 7 | |
| 8 | #define OMAP5_CLKCTRL_OFFSET 0x20 |
| 9 | #define OMAP5_CLKCTRL_INDEX(offset) ((offset) - OMAP5_CLKCTRL_OFFSET) |
| 10 | |
| 11 | /* mpu clocks */ |
| 12 | #define OMAP5_MPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) |
| 13 | |
| 14 | /* dsp clocks */ |
| 15 | #define OMAP5_MMU_DSP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) |
| 16 | |
| 17 | /* abe clocks */ |
| 18 | #define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) |
| 19 | #define OMAP5_AESS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) |
| 20 | #define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) |
| 21 | #define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) |
| 22 | #define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48) |
| 23 | #define OMAP5_MCBSP2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) |
| 24 | #define OMAP5_MCBSP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58) |
| 25 | #define OMAP5_TIMER5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) |
| 26 | #define OMAP5_TIMER6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70) |
| 27 | #define OMAP5_TIMER7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) |
| 28 | #define OMAP5_TIMER8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80) |
| 29 | |
| 30 | /* l3main1 clocks */ |
| 31 | #define OMAP5_L3_MAIN_1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) |
| 32 | |
| 33 | /* l3main2 clocks */ |
| 34 | #define OMAP5_L3_MAIN_2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) |
| 35 | |
| 36 | /* ipu clocks */ |
| 37 | #define OMAP5_MMU_IPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) |
| 38 | |
| 39 | /* dma clocks */ |
| 40 | #define OMAP5_DMA_SYSTEM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) |
| 41 | |
| 42 | /* emif clocks */ |
| 43 | #define OMAP5_DMM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) |
| 44 | #define OMAP5_EMIF1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) |
| 45 | #define OMAP5_EMIF2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) |
| 46 | |
| 47 | /* l4cfg clocks */ |
| 48 | #define OMAP5_L4_CFG_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) |
| 49 | #define OMAP5_SPINLOCK_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) |
| 50 | #define OMAP5_MAILBOX_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) |
| 51 | |
| 52 | /* l3instr clocks */ |
| 53 | #define OMAP5_L3_MAIN_3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) |
| 54 | #define OMAP5_L3_INSTR_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) |
| 55 | |
| 56 | /* l4per clocks */ |
| 57 | #define OMAP5_TIMER10_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) |
| 58 | #define OMAP5_TIMER11_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) |
| 59 | #define OMAP5_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) |
| 60 | #define OMAP5_TIMER3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40) |
| 61 | #define OMAP5_TIMER4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48) |
| 62 | #define OMAP5_TIMER9_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) |
| 63 | #define OMAP5_GPIO2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x60) |
| 64 | #define OMAP5_GPIO3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) |
| 65 | #define OMAP5_GPIO4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70) |
| 66 | #define OMAP5_GPIO5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) |
| 67 | #define OMAP5_GPIO6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80) |
| 68 | #define OMAP5_I2C1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa0) |
| 69 | #define OMAP5_I2C2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa8) |
| 70 | #define OMAP5_I2C3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb0) |
| 71 | #define OMAP5_I2C4_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb8) |
| 72 | #define OMAP5_L4_PER_CLKCTRL OMAP5_CLKCTRL_INDEX(0xc0) |
| 73 | #define OMAP5_MCSPI1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0) |
| 74 | #define OMAP5_MCSPI2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf8) |
| 75 | #define OMAP5_MCSPI3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x100) |
| 76 | #define OMAP5_MCSPI4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x108) |
| 77 | #define OMAP5_GPIO7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x110) |
| 78 | #define OMAP5_GPIO8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x118) |
| 79 | #define OMAP5_MMC3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x120) |
| 80 | #define OMAP5_MMC4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x128) |
| 81 | #define OMAP5_UART1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x140) |
| 82 | #define OMAP5_UART2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x148) |
| 83 | #define OMAP5_UART3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x150) |
| 84 | #define OMAP5_UART4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x158) |
| 85 | #define OMAP5_MMC5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x160) |
| 86 | #define OMAP5_I2C5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x168) |
| 87 | #define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170) |
| 88 | #define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178) |
| 89 | |
| 90 | /* l4_secure clocks */ |
| 91 | #define OMAP5_L4_SECURE_CLKCTRL_OFFSET 0x1a0 |
| 92 | #define OMAP5_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP5_L4_SECURE_CLKCTRL_OFFSET) |
| 93 | #define OMAP5_AES1_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a0) |
| 94 | #define OMAP5_AES2_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a8) |
| 95 | #define OMAP5_DES3DES_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b0) |
| 96 | #define OMAP5_FPKA_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b8) |
| 97 | #define OMAP5_RNG_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c0) |
| 98 | #define OMAP5_SHA2MD5_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c8) |
| 99 | #define OMAP5_DMA_CRYPTO_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1d8) |
| 100 | |
| 101 | /* iva clocks */ |
| 102 | #define OMAP5_IVA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) |
| 103 | #define OMAP5_SL2IF_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) |
| 104 | |
| 105 | /* dss clocks */ |
| 106 | #define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) |
| 107 | |
| 108 | /* gpu clocks */ |
| 109 | #define OMAP5_GPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) |
| 110 | |
| 111 | /* l3init clocks */ |
| 112 | #define OMAP5_MMC1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) |
| 113 | #define OMAP5_MMC2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) |
| 114 | #define OMAP5_USB_HOST_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58) |
| 115 | #define OMAP5_USB_TLL_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) |
| 116 | #define OMAP5_SATA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x88) |
| 117 | #define OMAP5_OCP2SCP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe0) |
| 118 | #define OMAP5_OCP2SCP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe8) |
| 119 | #define OMAP5_USB_OTG_SS_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0) |
| 120 | |
| 121 | /* wkupaon clocks */ |
| 122 | #define OMAP5_L4_WKUP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) |
| 123 | #define OMAP5_WD_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) |
| 124 | #define OMAP5_GPIO1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) |
| 125 | #define OMAP5_TIMER1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40) |
| 126 | #define OMAP5_COUNTER_32K_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) |
| 127 | #define OMAP5_KBD_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) |
| 128 | |
| 129 | #endif |