| Siva Durga Prasad Paladugu | b739897 | 2019-08-05 15:54:59 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * (C) Copyright 2019 Xilinx, Inc, |
| 4 | * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
| 5 | */ |
| 6 | |
| 7 | #ifndef _VERSALPL_H_ |
| 8 | #define _VERSALPL_H_ |
| 9 | |
| 10 | #include <xilinx.h> |
| 11 | |
| 12 | #define VERSAL_PM_LOAD_PDI 0x701 |
| 13 | #define VERSAL_PM_PDI_TYPE 0xF |
| 14 | |
| 15 | extern struct xilinx_fpga_op versal_op; |
| 16 | |
| 17 | #define XILINX_VERSAL_DESC \ |
| 18 | { xilinx_versal, csu_dma, 1, &versal_op, 0, &versal_op } |
| 19 | |
| 20 | #endif /* _VERSALPL_H_ */ |