| Stefan Roese | 95ca5fa | 2010-09-11 09:31:43 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2010 |
| 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 4 | * |
| Wolfgang Denk | bd8ec7e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| Stefan Roese | 95ca5fa | 2010-09-11 09:31:43 +0200 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef _PPC460SX_H_ |
| 9 | #define _PPC460SX_H_ |
| 10 | |
| 11 | #define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ |
| 12 | |
| Stefan Roese | 3ddce57 | 2010-09-20 16:05:31 +0200 | [diff] [blame] | 13 | /* Memory mapped registers */ |
| 14 | #define CONFIG_SYS_PERIPHERAL_BASE 0xa0000000 /* Internal Peripherals */ |
| 15 | |
| 16 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200) |
| 17 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) |
| 18 | |
| 19 | #define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700) |
| Stefan Roese | 95ca5fa | 2010-09-11 09:31:43 +0200 | [diff] [blame] | 20 | |
| 21 | #define SDR0_SRST0_DMC 0x00200000 |
| 22 | |
| 23 | #define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */ |
| 24 | #define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */ |
| 25 | #define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */ |
| 26 | #define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */ |
| 27 | #define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000 /* PLB Early Clock Divisor */ |
| 28 | #define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ |
| 29 | #define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */ |
| 30 | |
| 31 | #endif /* _PPC460SX_H_ */ |