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git01.mediatek.com / filogic / uboot / 06c91f0513cf758610971f8285600c336a13ed91 / . / arch / arm / dts / imx6qdl-gw53xx.dtsi
blob: 77ac103c2d9f494945a4582348e75a5c7f504453 [file] [log] [blame]
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2013 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/linux-event-codes.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9
10/ {
11 /* these are used by bootloader for disabling nodes */
12 aliases {
13 led0 = &led0;
14 led1 = &led1;
15 led2 = &led2;
Tim Harveycf08d1b2021-03-01 14:33:35 -0800[diff] [blame]16 mmc0 = &usdhc3;
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]17 nand = &gpmi;
18 ssi0 = &ssi1;
Tim Harvey69a53212021-07-24 10:40:36 -0700[diff] [blame]19 usb0 = &usbotg;
20 usb1 = &usbh1;
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]21 };
22
23 chosen {
24 bootargs = "console=ttymxc1,115200";
25 };
26
27 backlight {
28 compatible = "pwm-backlight";
29 pwms = <&pwm4 0 5000000>;
30 brightness-levels = <0 4 8 16 32 64 128 255>;
31 default-brightness-level = <7>;
32 };
33
34 gpio-keys {
35 compatible = "gpio-keys";
36 #address-cells = <1>;
37 #size-cells = <0>;
38
39 user-pb {
40 label = "user_pb";
41 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
42 linux,code = <BTN_0>;
43 };
44
45 user-pb1x {
46 label = "user_pb1x";
47 linux,code = <BTN_1>;
48 interrupt-parent = <&gsc>;
49 interrupts = <0>;
50 };
51
52 key-erased {
53 label = "key-erased";
54 linux,code = <BTN_2>;
55 interrupt-parent = <&gsc>;
56 interrupts = <1>;
57 };
58
59 eeprom-wp {
60 label = "eeprom_wp";
61 linux,code = <BTN_3>;
62 interrupt-parent = <&gsc>;
63 interrupts = <2>;
64 };
65
66 tamper {
67 label = "tamper";
68 linux,code = <BTN_4>;
69 interrupt-parent = <&gsc>;
70 interrupts = <5>;
71 };
72
73 switch-hold {
74 label = "switch_hold";
75 linux,code = <BTN_5>;
76 interrupt-parent = <&gsc>;
77 interrupts = <7>;
78 };
79 };
80
81 leds {
82 compatible = "gpio-leds";
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_gpio_leds>;
85
86 led0: user1 {
87 label = "user1";
88 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
89 default-state = "on";
90 linux,default-trigger = "heartbeat";
91 };
92
93 led1: user2 {
94 label = "user2";
95 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
96 default-state = "off";
97 };
98
99 led2: user3 {
100 label = "user3";
101 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
102 default-state = "off";
103 };
104 };
105
106 memory@10000000 {
107 device_type = "memory";
108 reg = <0x10000000 0x40000000>;
109 };
110
111 pps {
112 compatible = "pps-gpio";
113 pinctrl-names = "default";
114 pinctrl-0 = <&pinctrl_pps>;
115 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
116 status = "okay";
117 };
118
119 reg_1p0v: regulator-1p0v {
120 compatible = "regulator-fixed";
121 regulator-name = "1P0V";
122 regulator-min-microvolt = <1000000>;
123 regulator-max-microvolt = <1000000>;
124 regulator-always-on;
125 };
126
127 reg_3p3v: regulator-3p3v {
128 compatible = "regulator-fixed";
129 regulator-name = "3P3V";
130 regulator-min-microvolt = <3300000>;
131 regulator-max-microvolt = <3300000>;
132 regulator-always-on;
133 };
134
135 reg_usb_h1_vbus: regulator-usb-h1-vbus {
136 compatible = "regulator-fixed";
137 regulator-name = "usb_h1_vbus";
138 regulator-min-microvolt = <5000000>;
139 regulator-max-microvolt = <5000000>;
Tim Harvey469611e2021-09-29 15:04:22 -0700[diff] [blame]140 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
141 enable-active-high;
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]142 };
143
144 reg_usb_otg_vbus: regulator-usb-otg-vbus {
145 compatible = "regulator-fixed";
146 regulator-name = "usb_otg_vbus";
147 regulator-min-microvolt = <5000000>;
148 regulator-max-microvolt = <5000000>;
149 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
150 enable-active-high;
151 };
152
153 sound {
154 compatible = "fsl,imx6q-ventana-sgtl5000",
155 "fsl,imx-audio-sgtl5000";
156 model = "sgtl5000-audio";
157 ssi-controller = <&ssi1>;
158 audio-codec = <&codec>;
159 audio-routing =
160 "MIC_IN", "Mic Jack",
161 "Mic Jack", "Mic Bias",
162 "Headphone Jack", "HP_OUT";
163 mux-int-port = <1>;
164 mux-ext-port = <4>;
165 };
166};
167
168&audmux {
169 pinctrl-names = "default";
170 pinctrl-0 = <&pinctrl_audmux>;
171 status = "okay";
172};
173
174&can1 {
175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_flexcan1>;
177 status = "okay";
178};
179
180&clks {
181 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
182 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
183 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
184 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
185};
186
187&fec {
188 pinctrl-names = "default";
189 pinctrl-0 = <&pinctrl_enet>;
190 phy-mode = "rgmii-id";
191 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
Tim Harvey6ce10d52021-05-03 11:21:27 -0700[diff] [blame]192 phy-reset-duration = <10>;
193 phy-reset-post-delay = <100>;
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]194 status = "okay";
195};
196
197&gpmi {
198 pinctrl-names = "default";
199 pinctrl-0 = <&pinctrl_gpmi_nand>;
200 status = "okay";
201};
202
203&hdmi {
204 ddc-i2c-bus = <&i2c3>;
205 status = "okay";
206};
207
208&i2c1 {
209 clock-frequency = <100000>;
210 pinctrl-names = "default";
211 pinctrl-0 = <&pinctrl_i2c1>;
212 status = "okay";
213
214 gsc: gsc@20 {
215 compatible = "gw,gsc";
216 reg = <0x20>;
217 interrupt-parent = <&gpio1>;
218 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
219 interrupt-controller;
220 #interrupt-cells = <1>;
221 #size-cells = <0>;
222
223 adc {
224 compatible = "gw,gsc-adc";
225 #address-cells = <1>;
226 #size-cells = <0>;
227
228 channel@0 {
229 gw,mode = <0>;
230 reg = <0x00>;
231 label = "temp";
232 };
233
234 channel@2 {
235 gw,mode = <1>;
236 reg = <0x02>;
237 label = "vdd_vin";
238 };
239
240 channel@5 {
241 gw,mode = <1>;
242 reg = <0x05>;
243 label = "vdd_3p3";
244 };
245
246 channel@8 {
247 gw,mode = <1>;
248 reg = <0x08>;
249 label = "vdd_bat";
250 };
251
252 channel@b {
253 gw,mode = <1>;
254 reg = <0x0b>;
255 label = "vdd_5p0";
256 };
257
258 channel@e {
259 gw,mode = <1>;
260 reg = <0xe>;
261 label = "vdd_arm";
262 };
263
264 channel@11 {
265 gw,mode = <1>;
266 reg = <0x11>;
267 label = "vdd_soc";
268 };
269
270 channel@14 {
271 gw,mode = <1>;
272 reg = <0x14>;
273 label = "vdd_3p0";
274 };
275
276 channel@17 {
277 gw,mode = <1>;
278 reg = <0x17>;
279 label = "vdd_1p5";
280 };
281
282 channel@1d {
283 gw,mode = <1>;
284 reg = <0x1d>;
285 label = "vdd_1p8";
286 };
287
288 channel@20 {
289 gw,mode = <1>;
290 reg = <0x20>;
291 label = "vdd_1p0";
292 };
293
294 channel@23 {
295 gw,mode = <1>;
296 reg = <0x23>;
297 label = "vdd_2p5";
298 };
299
300 channel@26 {
301 gw,mode = <1>;
302 reg = <0x26>;
303 label = "vdd_gps";
304 };
305
306 channel@29 {
307 gw,mode = <1>;
308 reg = <0x29>;
309 label = "vdd_an1";
310 };
311 };
312 };
313
314 gsc_gpio: gpio@23 {
315 compatible = "nxp,pca9555";
316 reg = <0x23>;
317 gpio-controller;
318 #gpio-cells = <2>;
319 interrupt-parent = <&gsc>;
320 interrupts = <4>;
321 };
322
323 eeprom1: eeprom@50 {
324 compatible = "atmel,24c02";
325 reg = <0x50>;
326 pagesize = <16>;
327 };
328
329 eeprom2: eeprom@51 {
330 compatible = "atmel,24c02";
331 reg = <0x51>;
332 pagesize = <16>;
333 };
334
335 eeprom3: eeprom@52 {
336 compatible = "atmel,24c02";
337 reg = <0x52>;
338 pagesize = <16>;
339 };
340
341 eeprom4: eeprom@53 {
342 compatible = "atmel,24c02";
343 reg = <0x53>;
344 pagesize = <16>;
345 };
346
347 rtc: ds1672@68 {
348 compatible = "dallas,ds1672";
349 reg = <0x68>;
350 };
351};
352
353&i2c2 {
354 clock-frequency = <100000>;
355 pinctrl-names = "default";
356 pinctrl-0 = <&pinctrl_i2c2>;
357 status = "okay";
358
359 ltc3676: pmic@3c {
360 compatible = "lltc,ltc3676";
361 reg = <0x3c>;
362 interrupt-parent = <&gpio1>;
363 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
364
365 regulators {
366 /* VDD_SOC (1+R1/R2 = 1.635) */
367 reg_vdd_soc: sw1 {
368 regulator-name = "vddsoc";
369 regulator-min-microvolt = <674400>;
370 regulator-max-microvolt = <1308000>;
371 lltc,fb-voltage-divider = <127000 200000>;
372 regulator-ramp-delay = <7000>;
373 regulator-boot-on;
374 regulator-always-on;
375 };
376
377 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
378 reg_1p8v: sw2 {
379 regulator-name = "vdd1p8";
380 regulator-min-microvolt = <1033310>;
381 regulator-max-microvolt = <2004000>;
382 lltc,fb-voltage-divider = <301000 200000>;
383 regulator-ramp-delay = <7000>;
384 regulator-boot-on;
385 regulator-always-on;
386 };
387
388 /* VDD_ARM (1+R1/R2 = 1.635) */
389 reg_vdd_arm: sw3 {
390 regulator-name = "vddarm";
391 regulator-min-microvolt = <674400>;
392 regulator-max-microvolt = <1308000>;
393 lltc,fb-voltage-divider = <127000 200000>;
394 regulator-ramp-delay = <7000>;
395 regulator-boot-on;
396 regulator-always-on;
397 };
398
399 /* VDD_DDR (1+R1/R2 = 2.105) */
400 reg_vdd_ddr: sw4 {
401 regulator-name = "vddddr";
402 regulator-min-microvolt = <868310>;
403 regulator-max-microvolt = <1684000>;
404 lltc,fb-voltage-divider = <221000 200000>;
405 regulator-ramp-delay = <7000>;
406 regulator-boot-on;
407 regulator-always-on;
408 };
409
410 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
411 reg_2p5v: ldo2 {
412 regulator-name = "vdd2p5";
413 regulator-min-microvolt = <2490375>;
414 regulator-max-microvolt = <2490375>;
415 lltc,fb-voltage-divider = <487000 200000>;
416 regulator-boot-on;
417 regulator-always-on;
418 };
419
420 /* VDD_AUD_1P8: Audio codec */
421 reg_aud_1p8v: ldo3 {
422 regulator-name = "vdd1p8a";
423 regulator-min-microvolt = <1800000>;
424 regulator-max-microvolt = <1800000>;
425 regulator-boot-on;
426 };
427
428 /* VDD_HIGH (1+R1/R2 = 4.17) */
429 reg_3p0v: ldo4 {
430 regulator-name = "vdd3p0";
431 regulator-min-microvolt = <3023250>;
432 regulator-max-microvolt = <3023250>;
433 lltc,fb-voltage-divider = <634000 200000>;
434 regulator-boot-on;
435 regulator-always-on;
436 };
437 };
438 };
439};
440
441&i2c3 {
442 clock-frequency = <100000>;
443 pinctrl-names = "default";
444 pinctrl-0 = <&pinctrl_i2c3>;
445 status = "okay";
446
447 codec: sgtl5000@a {
448 compatible = "fsl,sgtl5000";
449 reg = <0x0a>;
450 clocks = <&clks IMX6QDL_CLK_CKO>;
451 VDDA-supply = <&reg_1p8v>;
452 VDDIO-supply = <&reg_3p3v>;
453 };
454
455 touchscreen: egalax_ts@4 {
456 compatible = "eeti,egalax_ts";
457 reg = <0x04>;
458 interrupt-parent = <&gpio1>;
459 interrupts = <11 2>;
460 wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
461 };
462
463 accel@1e {
464 compatible = "nxp,fxos8700";
465 reg = <0x1e>;
466 };
467};
468
469&ldb {
470 status = "okay";
471
472 lvds-channel@0 {
473 fsl,data-mapping = "spwg";
474 fsl,data-width = <18>;
475 status = "okay";
476
477 display-timings {
478 native-mode = <&timing0>;
479 timing0: hsd100pxn1 {
480 clock-frequency = <65000000>;
481 hactive = <1024>;
482 vactive = <768>;
483 hback-porch = <220>;
484 hfront-porch = <40>;
485 vback-porch = <21>;
486 vfront-porch = <7>;
487 hsync-len = <60>;
488 vsync-len = <10>;
489 };
490 };
491 };
492};
493
494&pcie {
495 pinctrl-names = "default";
496 pinctrl-0 = <&pinctrl_pcie>;
497 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
498 status = "okay";
499};
500
501&pwm2 {
502 pinctrl-names = "default";
503 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
504 status = "disabled";
505};
506
507&pwm3 {
508 pinctrl-names = "default";
509 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
510 status = "disabled";
511};
512
513&pwm4 {
514 #pwm-cells = <2>;
515 pinctrl-names = "default";
516 pinctrl-0 = <&pinctrl_pwm4>;
517 status = "okay";
518};
519
520&ssi1 {
521 status = "okay";
522};
523
524&uart1 {
525 pinctrl-names = "default";
526 pinctrl-0 = <&pinctrl_uart1>;
527 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
528 status = "okay";
529};
530
531&uart2 {
532 pinctrl-names = "default";
533 pinctrl-0 = <&pinctrl_uart2>;
534 status = "okay";
535};
536
537&uart5 {
538 pinctrl-names = "default";
539 pinctrl-0 = <&pinctrl_uart5>;
540 status = "okay";
541};
542
543&usbotg {
544 vbus-supply = <&reg_usb_otg_vbus>;
545 pinctrl-names = "default";
546 pinctrl-0 = <&pinctrl_usbotg>;
547 disable-over-current;
Tim Harvey3deb9892021-03-01 14:33:31 -0800[diff] [blame]548 dr_mode = "otg";
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]549 status = "okay";
550};
551
552&usbh1 {
553 vbus-supply = <&reg_usb_h1_vbus>;
Tim Harvey469611e2021-09-29 15:04:22 -0700[diff] [blame]554 pinctrl-names = "default";
555 pinctrl-0 = <&pinctrl_usbh1>;
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]556 status = "okay";
557};
558
559&usdhc3 {
560 pinctrl-names = "default", "state_100mhz", "state_200mhz";
561 pinctrl-0 = <&pinctrl_usdhc3>;
562 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
563 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
564 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
565 vmmc-supply = <&reg_3p3v>;
566 no-1-8-v; /* firmware will remove if board revision supports */
567 status = "okay";
568};
569
570&wdog1 {
571 pinctrl-names = "default";
572 pinctrl-0 = <&pinctrl_wdog>;
573 fsl,ext-reset-output;
574};
575
576&iomuxc {
577 pinctrl_audmux: audmuxgrp {
578 fsl,pins = <
579 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
580 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
581 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
582 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
583 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
584 >;
585 };
586
587 pinctrl_enet: enetgrp {
588 fsl,pins = <
589 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
590 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
591 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
592 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
593 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
594 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
595 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
596 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
597 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
598 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
599 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
600 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
601 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
602 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
603 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
604 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
Tim Harvey6ce10d52021-05-03 11:21:27 -0700[diff] [blame]605 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]606 >;
607 };
608
609 pinctrl_flexcan1: flexcan1grp {
610 fsl,pins = <
611 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
612 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
613 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
614 >;
615 };
616
617 pinctrl_gpio_leds: gpioledsgrp {
618 fsl,pins = <
619 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
620 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
621 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
622 >;
623 };
624
625 pinctrl_gpmi_nand: gpminandgrp {
626 fsl,pins = <
627 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
628 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
629 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
630 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
631 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
632 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
633 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
634 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
635 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
636 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
637 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
638 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
639 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
640 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
641 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
642 >;
643 };
644
645 pinctrl_i2c1: i2c1grp {
646 fsl,pins = <
647 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
648 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
649 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
650 >;
651 };
652
653 pinctrl_i2c2: i2c2grp {
654 fsl,pins = <
655 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
656 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
657 >;
658 };
659
660 pinctrl_i2c3: i2c3grp {
661 fsl,pins = <
662 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
663 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
664 >;
665 };
666
667 pinctrl_pcie: pciegrp {
668 fsl,pins = <
669 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
670 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
671 >;
672 };
673
674 pinctrl_pmic: pmicgrp {
675 fsl,pins = <
676 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
677 >;
678 };
679
680 pinctrl_pps: ppsgrp {
681 fsl,pins = <
682 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
683 >;
684 };
685
686 pinctrl_pwm2: pwm2grp {
687 fsl,pins = <
688 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
689 >;
690 };
691
692 pinctrl_pwm3: pwm3grp {
693 fsl,pins = <
694 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
695 >;
696 };
697
698 pinctrl_pwm4: pwm4grp {
699 fsl,pins = <
700 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
701 >;
702 };
703
704 pinctrl_uart1: uart1grp {
705 fsl,pins = <
706 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
707 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
708 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
709 >;
710 };
711
712 pinctrl_uart2: uart2grp {
713 fsl,pins = <
714 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
715 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
716 >;
717 };
718
719 pinctrl_uart5: uart5grp {
720 fsl,pins = <
721 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
722 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
723 >;
724 };
725
Tim Harvey469611e2021-09-29 15:04:22 -0700[diff] [blame]726 pinctrl_usbh1: usbh1grp {
727 fsl,pins = <
728 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
729 >;
730 };
731
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]732 pinctrl_usbotg: usbotggrp {
733 fsl,pins = <
734 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
735 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
736 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
737 >;
738 };
739
740 pinctrl_usdhc3: usdhc3grp {
741 fsl,pins = <
742 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
743 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
744 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
745 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
746 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
747 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
748 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
749 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
750 >;
751 };
752
753 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
754 fsl,pins = <
755 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
756 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
757 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
758 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
759 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
760 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
761 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
762 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
763 >;
764 };
765
766 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
767 fsl,pins = <
768 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
769 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
770 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
771 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
772 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
773 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
774 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
775 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
776 >;
777 };
778
779 pinctrl_wdog: wdoggrp {
780 fsl,pins = <
781 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
782 >;
783 };
784};