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git01.mediatek.com / filogic / uboot / 06b5171ecfc1786ebddba52039c85f87adb20550 / . / arch / mips / mach-mtmips / mt7621 / spl / dram.c
blob: 100adfb93a57187f772b12d225a10d30b6a891c3 [file] [log] [blame]
developer2fddd722022-05-20 11:22:21 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2022 MediaTek Inc. All rights reserved.
4 *
5 * Author: Weijie Gao <weijie.gao@mediatek.com>
6 */
7
8#include <vsprintf.h>
9#include <asm/io.h>
10#include <asm/sections.h>
11#include <asm/byteorder.h>
12#include <asm/addrspace.h>
13#include <linux/string.h>
14#include "../mt7621.h"
15#include "dram.h"
16
17static const u32 ddr2_act[DDR_PARAM_SIZE] = {
18#if defined(CONFIG_MT7621_DRAM_DDR2_512M)
19 0xAA00AA00, 0xAA00AA00, 0x00000007, 0x22174441,
20 0x00000000, 0xF0748661, 0x40001273, 0x9F0A0481,
21 0x0304692F, 0x15602842, 0x00008888, 0x88888888,
22 0x00000000, 0x00000000, 0x00000000, 0x07100000,
23 0x00001B63, 0x00002000, 0x00004000, 0x00006000,
24 0x00000000, 0x00000000, 0x00000000, 0x00000000,
25#elif defined(CONFIG_MT7621_DRAM_DDR2_512M_W9751G6KB_A02_1066MHZ)
26 0xAA00AA00, 0xAA00AA00, 0x00000007, 0x33484584,
27 0x00000000, 0xF07486A1, 0x50001273, 0x9F010481,
28 0x0304693F, 0x15602842, 0x00008888, 0x88888888,
29 0x00000000, 0x00000000, 0x00000010, 0x07100000,
30 0x00001F73, 0x00002000, 0x00004000, 0x00006000,
31 0x00000000, 0x00000000, 0x00000000, 0x00000000,
32#elif defined(CONFIG_MT7621_DRAM_DDR2_1024M_W971GG6KB25_800MHZ)
33 0xAA00AA00, 0xAA00AA00, 0x00000007, 0x22174430,
34 0x01000000, 0xF0748661, 0x40001273, 0x9F0F0481,
35 0x0304692F, 0x15602842, 0x00008888, 0x88888888,
36 0x00000000, 0x00000000, 0x00000000, 0x07100000,
37 0x00001B63, 0x00002000, 0x00004000, 0x00006000,
38 0x00000000, 0x00000000, 0x00000000, 0x00000000,
39#elif defined(CONFIG_MT7621_DRAM_DDR2_1024M_W971GG6KB18_1066MHZ)
40 0xAA00AA00, 0xAA00AA00, 0x00000007, 0x33484584,
41 0x01000000, 0xF07486A1, 0x50001273, 0x9F070481,
42 0x0304693F, 0x15602842, 0x00008888, 0x88888888,
43 0x00000000, 0x00000000, 0x00000010, 0x07100000,
44 0x00001F73, 0x00002000, 0x00004000, 0x00006000,
45 0x00000000, 0x00000000, 0x00000000, 0x00000000,
46#else /* CONFIG_MT7621_DRAM_DDR2_1024M */
47 0xAA00AA00, 0xAA00AA00, 0x00000007, 0x22174441,
48 0x01000000, 0xF0748661, 0x40001273, 0x9F0F0481,
49 0x0304692F, 0x15602842, 0x00008888, 0x88888888,
50 0x00000000, 0x00000000, 0x00000000, 0x07100000,
51 0x00001B63, 0x00002000, 0x00004000, 0x00006000,
52 0x00000000, 0x00000000, 0x00000000, 0x00000000,
53#endif
54};
55
56static const u32 ddr3_act[DDR_PARAM_SIZE] = {
57#if defined(CONFIG_MT7621_DRAM_DDR3_1024M)
58 0xAA00AA00, 0xAA00AA00, 0x00000007, 0x44694683,
59 0x01000000, 0xF07486A1, 0xC287221D, 0x9F060481,
60 0x03046948, 0x15602842, 0x00008888, 0x88888888,
61 0x00000000, 0x00000000, 0x00000210, 0x07100000,
62 0x00001B61, 0x00002040, 0x00004010, 0x00006000,
63 0x0C000000, 0x07070000, 0x00000000, 0x00000000,
64#elif defined(CONFIG_MT7621_DRAM_DDR3_4096M)
65 0xAA00AA00, 0xAA00AA00, 0x00000007, 0x44694683,
66 0x01000000, 0xF07486A1, 0xC287221D, 0x9F0F0481,
67 0x03046948, 0x15602842, 0x00008888, 0x88888888,
68 0x00000000, 0x00000000, 0x00000240, 0x07100000,
69 0x00001B61, 0x00002040, 0x00004010, 0x00006000,
70 0x0C000000, 0x07070000, 0x00000000, 0x00000000,
71#elif defined(CONFIG_MT7621_DRAM_DDR3_1024M_KGD)
72 0xFF00FF00, 0xFF00FF00, 0x00000007, 0x44694683,
73 0x01000000, 0xF07406A1, 0xC287221D, 0x9F060481,
74 0x03046923, 0x152f2842, 0x00008888, 0x88888888,
75 0x00000000, 0x00000000, 0x00000210, 0x07100000,
76 0x00001B61, 0x00002040, 0x00004010, 0x00006000,
77 0x0C000000, 0x07070000, 0x000C0000, 0x00000000,
78#else /* CONFIG_MT7621_DRAM_DDR3_2048M */
79 0xAA00AA00, 0xAA00AA00, 0x00000007, 0x44694673,
80 0x01000000, 0xF07486A1, 0xC287221D, 0x9F050481,
81 0x03046948, 0x15602842, 0x00008888, 0x88888888,
82 0x00000000, 0x00000000, 0x00000220, 0x07100000,
83 0x00001B61, 0x00002040, 0x00004010, 0x00006000,
84 0x0C000000, 0x07070000, 0x00000000, 0x00000000,
85#endif
86};
87
88#if defined(CONFIG_MT7621_DRAM_FREQ_400)
89#define DDR_FREQ_PARAM 0x41000000
90#elif defined(CONFIG_MT7621_DRAM_FREQ_1066)
91#define DDR_FREQ_PARAM 0x21000000
92#elif defined(CONFIG_MT7621_DRAM_FREQ_1200)
93#define DDR_FREQ_PARAM 0x11000000
94#else /* CONFIG_MT7621_DRAM_FREQ_800 */
95#define DDR_FREQ_PARAM 0x31000000
96#endif
97
98#define RG_MEPL_FBDIV_S 4
99#define RG_MEPL_FBDIV_M 0x7f
100
101static inline void word_copy(u32 *dest, const u32 *src, u32 count)
102{
103 u32 i;
104
105 for (i = 0; i < count; i++)
106 dest[i] = src[i];
107}
108
109static u32 calc_cpu_pll_val(void)
110{
111 u32 div, baseval, fb;
112
113 div = get_xtal_mhz();
114
115 if (div == 40) {
116 div /= 2;
117 baseval = 0xc0005802;
118 } else {
119 baseval = 0xc0004802;
120 }
121
122 fb = CONFIG_MT7621_CPU_FREQ / div - 1;
123 if (fb > RG_MEPL_FBDIV_M)
124 fb = RG_MEPL_FBDIV_M;
125
126 return baseval | (fb << RG_MEPL_FBDIV_S);
127}
128
129void prepare_stage_bin(void)
130{
131 u32 stage_size;
132
133 const struct stage_header *stock_stage_bin =
134 (const struct stage_header *)__image_copy_end;
135
136 struct stage_header *new_stage_bin =
137 (struct stage_header *)STAGE_LOAD_ADDR;
138
139 if (be32_to_cpu(stock_stage_bin->ep) != STAGE_LOAD_ADDR)
140 panic("Invalid DDR stage binary blob\n");
141
142 stage_size = be32_to_cpu(stock_stage_bin->stage_size);
143
144 word_copy((u32 *)new_stage_bin, (const u32 *)stock_stage_bin,
145 (stage_size + sizeof(u32) - 1) / sizeof(u32));
146
147 word_copy(new_stage_bin->ddr2_act, ddr2_act, DDR_PARAM_SIZE);
148 word_copy(new_stage_bin->ddr3_act, ddr3_act, DDR_PARAM_SIZE);
149
150 new_stage_bin->cpu_pll_cfg = calc_cpu_pll_val();
151 new_stage_bin->ddr_pll_cfg = DDR_FREQ_PARAM;
152 new_stage_bin->baudrate = CONFIG_BAUDRATE;
153}