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git01.mediatek.com / filogic / uboot / 06a2234f7004de504d5e6883f293259e4e734bfc / . / drivers / clk / qcom / clock-sm8250.c
blob: e322a923a5c048769dd5134c6c24e16bb74e7317 [file] [log] [blame]
Caleb Connolly78672c62024-04-08 15:06:51 +0200[diff] [blame]1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * Clock drivers for Qualcomm sm8250
4 *
5 * (C) Copyright 2024 Linaro Ltd.
6 */
7
8#include <clk-uclass.h>
9#include <dm.h>
10#include <linux/delay.h>
11#include <asm/io.h>
12#include <linux/bug.h>
13#include <linux/bitops.h>
14#include <dt-bindings/clock/qcom,gcc-sm8250.h>
15
16#include "clock-qcom.h"
17
18#define GCC_SE12_UART_RCG_REG 0x184D0
19#define GCC_SDCC2_APPS_CLK_SRC_REG 0x1400c
20
21#define APCS_GPLL0_ENA_VOTE 0x79000
22#define APCS_GPLL9_STATUS 0x1c000
23#define APCS_GPLLX_ENA_REG 0x52018
24
25#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020
26#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038
27#define USB3_PRIM_PHY_AUX_CMD_RCGR 0xf064
28
29static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s4_clk_src[] = {
30 F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
31 F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
32 F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
33 F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625),
34 F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
35 F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
36 F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0),
37 F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
38 F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
39 F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
40 F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
41 F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0),
42 {}
43};
44
45static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
46 F(400000, CFG_CLK_SRC_CXO, 12, 1, 4),
47 F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
48 F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
49 F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0),
50 F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0),
51 F(202000000, CFG_CLK_SRC_GPLL9, 4, 0, 0),
52 {}
53};
54
55static struct pll_vote_clk gpll9_vote_clk = {
56 .status = APCS_GPLL9_STATUS,
57 .status_bit = BIT(31),
58 .ena_vote = APCS_GPLLX_ENA_REG,
59 .vote_bit = BIT(9),
60};
61
62static ulong sm8250_set_rate(struct clk *clk, ulong rate)
63{
64 struct msm_clk_priv *priv = dev_get_priv(clk->dev);
65 const struct freq_tbl *freq;
66
67 if (clk->id < priv->data->num_clks)
68 debug("%s: %s, requested rate=%ld\n", __func__,
69 priv->data->clks[clk->id].name, rate);
70
71 switch (clk->id) {
72 case GCC_QUPV3_WRAP1_S4_CLK: /*UART2*/
73 freq = qcom_find_freq(ftbl_gcc_qupv3_wrap1_s4_clk_src, rate);
74 clk_rcg_set_rate_mnd(priv->base, GCC_SE12_UART_RCG_REG,
75 freq->pre_div, freq->m, freq->n, freq->src,
76 16);
77
78 return freq->freq;
79 case GCC_SDCC2_APPS_CLK:
80 /* Enable GPLL9 so that we can point SDCC2_APPS_CLK_SRC at it */
81 clk_enable_gpll0(priv->base, &gpll9_vote_clk);
82 freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate);
83 printf("%s: got freq %u\n", __func__, freq->freq);
84 WARN(freq->src != CFG_CLK_SRC_GPLL9,
85 "SDCC2_APPS_CLK_SRC not set to GPLL9, requested rate %lu\n",
86 rate);
87 clk_rcg_set_rate_mnd(priv->base, GCC_SDCC2_APPS_CLK_SRC_REG,
88 freq->pre_div, freq->m, freq->n,
89 CFG_CLK_SRC_GPLL9, 8);
90
91 return rate;
92 default:
93 return 0;
94 }
95}
96
97static const struct gate_clk sm8250_clks[] = {
98 GATE_CLK(GCC_AGGRE_UFS_CARD_AXI_CLK, 0x750cc, 0x00000001),
99 GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770cc, 0x00000001),
100 GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0x0f080, 0x00000001),
101 GATE_CLK(GCC_AGGRE_USB3_SEC_AXI_CLK, 0x10080, 0x00000001),
102 GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x0f07c, 0x00000001),
103 GATE_CLK(GCC_CFG_NOC_USB3_SEC_AXI_CLK, 0x1007c, 0x00000001),
104 GATE_CLK(GCC_QMIP_CAMERA_NRT_AHB_CLK, 0x0b018, 0x00000001),
105 GATE_CLK(GCC_QMIP_CAMERA_RT_AHB_CLK, 0x0b01c, 0x00000001),
106 GATE_CLK(GCC_QMIP_DISP_AHB_CLK, 0x0b020, 0x00000001),
107 GATE_CLK(GCC_QMIP_VIDEO_CVP_AHB_CLK, 0x0b010, 0x00000001),
108 GATE_CLK(GCC_QMIP_VIDEO_VCODEC_AHB_CLK, 0x0b014, 0x00000001),
109 GATE_CLK(GCC_QUPV3_WRAP0_CORE_2X_CLK, 0x52008, 0x00000200),
110 GATE_CLK(GCC_QUPV3_WRAP0_CORE_CLK, 0x52008, 0x00000100),
111 GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x52008, 0x00000400),
112 GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x52008, 0x00000800),
113 GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x52008, 0x00001000),
114 GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x52008, 0x00002000),
115 GATE_CLK(GCC_QUPV3_WRAP0_S4_CLK, 0x52008, 0x00004000),
116 GATE_CLK(GCC_QUPV3_WRAP0_S5_CLK, 0x52008, 0x00008000),
117 GATE_CLK(GCC_QUPV3_WRAP0_S6_CLK, 0x52008, 0x00010000),
118 GATE_CLK(GCC_QUPV3_WRAP0_S7_CLK, 0x52008, 0x00020000),
119 GATE_CLK(GCC_QUPV3_WRAP1_CORE_2X_CLK, 0x52008, 0x00040000),
120 GATE_CLK(GCC_QUPV3_WRAP1_CORE_CLK, 0x52008, 0x00080000),
121 GATE_CLK(GCC_QUPV3_WRAP1_S0_CLK, 0x52008, 0x00400000),
122 GATE_CLK(GCC_QUPV3_WRAP1_S1_CLK, 0x52008, 0x00800000),
123 GATE_CLK(GCC_QUPV3_WRAP1_S2_CLK, 0x52008, 0x01000000),
124 GATE_CLK(GCC_QUPV3_WRAP1_S3_CLK, 0x52008, 0x02000000),
125 GATE_CLK(GCC_QUPV3_WRAP1_S4_CLK, 0x52008, 0x04000000),
126 GATE_CLK(GCC_QUPV3_WRAP1_S5_CLK, 0x52008, 0x08000000),
127 GATE_CLK(GCC_QUPV3_WRAP2_CORE_2X_CLK, 0x52010, 0x00000008),
128 GATE_CLK(GCC_QUPV3_WRAP2_CORE_CLK, 0x52010, 0x00000001),
129 GATE_CLK(GCC_QUPV3_WRAP2_S0_CLK, 0x52010, 0x00000010),
130 GATE_CLK(GCC_QUPV3_WRAP2_S1_CLK, 0x52010, 0x00000020),
131 GATE_CLK(GCC_QUPV3_WRAP2_S2_CLK, 0x52010, 0x00000040),
132 GATE_CLK(GCC_QUPV3_WRAP2_S3_CLK, 0x52010, 0x00000080),
133 GATE_CLK(GCC_QUPV3_WRAP2_S4_CLK, 0x52010, 0x00000100),
134 GATE_CLK(GCC_QUPV3_WRAP2_S5_CLK, 0x52010, 0x00000200),
135 GATE_CLK(GCC_QUPV3_WRAP_0_M_AHB_CLK, 0x52008, 0x00000040),
136 GATE_CLK(GCC_QUPV3_WRAP_0_S_AHB_CLK, 0x52008, 0x00000080),
137 GATE_CLK(GCC_QUPV3_WRAP_1_M_AHB_CLK, 0x52008, 0x00100000),
138 GATE_CLK(GCC_QUPV3_WRAP_1_S_AHB_CLK, 0x52008, 0x00200000),
139 GATE_CLK(GCC_QUPV3_WRAP_2_M_AHB_CLK, 0x52010, 0x00000004),
140 GATE_CLK(GCC_QUPV3_WRAP_2_S_AHB_CLK, 0x52010, 0x00000002),
141 GATE_CLK(GCC_SDCC2_AHB_CLK, 0x14008, 0x00000001),
142 GATE_CLK(GCC_SDCC2_APPS_CLK, 0x14004, 0x00000001),
143 GATE_CLK(GCC_SDCC4_AHB_CLK, 0x16008, 0x00000001),
144 GATE_CLK(GCC_SDCC4_APPS_CLK, 0x16004, 0x00000001),
145 GATE_CLK(GCC_UFS_CARD_AHB_CLK, 0x75018, 0x00000001),
146 GATE_CLK(GCC_UFS_CARD_AXI_CLK, 0x75010, 0x00000001),
147 GATE_CLK(GCC_UFS_CARD_ICE_CORE_CLK, 0x75064, 0x00000001),
148 GATE_CLK(GCC_UFS_CARD_PHY_AUX_CLK, 0x7509c, 0x00000001),
149 GATE_CLK(GCC_UFS_CARD_RX_SYMBOL_0_CLK, 0x75020, 0x00000001),
150 GATE_CLK(GCC_UFS_CARD_RX_SYMBOL_1_CLK, 0x750b8, 0x00000001),
151 GATE_CLK(GCC_UFS_CARD_TX_SYMBOL_0_CLK, 0x7501c, 0x00000001),
152 GATE_CLK(GCC_UFS_CARD_UNIPRO_CORE_CLK, 0x7505c, 0x00000001),
153 GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77018, 0x00000001),
154 GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x77010, 0x00000001),
155 GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x77064, 0x00000001),
156 GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x7709c, 0x00000001),
157 GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x77020, 0x00000001),
158 GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_1_CLK, 0x770b8, 0x00000001),
159 GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x7701c, 0x00000001),
160 GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x7705c, 0x00000001),
161 GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x0f010, 0x00000001),
162 GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x0f01c, 0x00000001),
163 GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x0f018, 0x00000001),
164 GATE_CLK(GCC_USB30_SEC_MASTER_CLK, 0x10010, 0x00000001),
165 GATE_CLK(GCC_USB30_SEC_MOCK_UTMI_CLK, 0x1001c, 0x00000001),
166 GATE_CLK(GCC_USB30_SEC_SLEEP_CLK, 0x10018, 0x00000001),
167 GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x0f054, 0x00000001),
168 GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x0f058, 0x00000001),
169 GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x0f05c, 0x00000001),
170 GATE_CLK(GCC_USB3_SEC_CLKREF_EN, 0x8c010, 0x00000001),
171 GATE_CLK(GCC_USB3_SEC_PHY_AUX_CLK, 0x10054, 0x00000001),
172 GATE_CLK(GCC_USB3_SEC_PHY_COM_AUX_CLK, 0x10058, 0x00000001),
173 GATE_CLK(GCC_USB3_SEC_PHY_PIPE_CLK, 0x1005c, 0x00000001),
174};
175
176static int sm8250_enable(struct clk *clk)
177{
178 struct msm_clk_priv *priv = dev_get_priv(clk->dev);
179
180 if (priv->data->num_clks < clk->id) {
181 debug("%s: unknown clk id %lu\n", __func__, clk->id);
182 return 0;
183 }
184
185 debug("%s: clk %s\n", __func__, sm8250_clks[clk->id].name);
186
187 switch (clk->id) {
188 case GCC_USB30_PRIM_MASTER_CLK:
189 qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK);
190 qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK);
191 break;
192 case GCC_USB30_SEC_MASTER_CLK:
193 qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_AUX_CLK);
194 qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_COM_AUX_CLK);
195 break;
196 }
197
198 qcom_gate_clk_en(priv, clk->id);
199
200 return 0;
201}
202
203static const struct qcom_reset_map sm8250_gcc_resets[] = {
204 [GCC_GPU_BCR] = { 0x71000 },
205 [GCC_MMSS_BCR] = { 0xb000 },
206 [GCC_NPU_BWMON_BCR] = { 0x73000 },
207 [GCC_NPU_BCR] = { 0x4d000 },
208 [GCC_PCIE_0_BCR] = { 0x6b000 },
209 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
210 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
211 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
212 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
213 [GCC_PCIE_1_BCR] = { 0x8d000 },
214 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
215 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
216 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
217 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e000 },
218 [GCC_PCIE_2_BCR] = { 0x6000 },
219 [GCC_PCIE_2_LINK_DOWN_BCR] = { 0x1f014 },
220 [GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0x1f020 },
221 [GCC_PCIE_2_PHY_BCR] = { 0x1f01c },
222 [GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR] = { 0x1f028 },
223 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
224 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
225 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
226 [GCC_PDM_BCR] = { 0x33000 },
227 [GCC_PRNG_BCR] = { 0x34000 },
228 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
229 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
230 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
231 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
232 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
233 [GCC_SDCC2_BCR] = { 0x14000 },
234 [GCC_SDCC4_BCR] = { 0x16000 },
235 [GCC_TSIF_BCR] = { 0x36000 },
236 [GCC_UFS_CARD_BCR] = { 0x75000 },
237 [GCC_UFS_PHY_BCR] = { 0x77000 },
238 [GCC_USB30_PRIM_BCR] = { 0xf000 },
239 [GCC_USB30_SEC_BCR] = { 0x10000 },
240 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
241 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
242 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
243 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
244 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
245 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
246 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
247};
248
249static const struct qcom_power_map sm8250_gdscs[] = {
250 [PCIE_0_GDSC] = { 0x6b004 }, [PCIE_1_GDSC] = { 0x8d004 },
251 [PCIE_2_GDSC] = { 0x6004 }, [UFS_CARD_GDSC] = { 0x75004 },
252 [UFS_PHY_GDSC] = { 0x77004 }, [USB30_PRIM_GDSC] = { 0xf004 },
253 [USB30_SEC_GDSC] = { 0x10004 },
254};
255
Caleb Connollya17233d2024-08-19 21:34:20 +0200[diff] [blame]256static const phys_addr_t sm8250_gpll_addrs[] = {
257 0x00100000, // GCC_GPLL0_MODE
258 0x00101000, // GCC_GPLL1_MODE
259 0x00102000, // GCC_GPLL2_MODE
260 0x00103000, // GCC_GPLL3_MODE
261 0x00176000, // GCC_GPLL4_MODE
262 0x00174000, // GCC_GPLL5_MODE
263 0x00113000, // GCC_GPLL6_MODE
264 0x0011a000, // GCC_GPLL7_MODE
265 0x0011b000, // GCC_GPLL8_MODE
266 0x0011c000, // GCC_GPLL9_MODE
267 0x0011d000, // GCC_GPLL10_MODE
268 0x0014a000, // GCC_GPLL11_MODE
269};
270
271static const phys_addr_t sm8250_rcg_addrs[] = {
272 0x0010f020, // GCC_USB30_PRIM_MASTER_CMD_RCGR
273 0x0010f038, // GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR
274 0x0010f064, // GCC_USB3_PRIM_PHY_AUX_CMD_RCGR
275 0x00110020, // GCC_USB30_SEC_MASTER_CMD_RCGR
276 0x00110038, // GCC_USB30_SEC_MOCK_UTMI_CMD_RCGR
277 0x00110064, // GCC_USB3_SEC_PHY_AUX_CMD_RCGR
278 0x0011400c, // GCC_SDCC2_APPS_CMD_RCGR
279 0x0011600c, // GCC_SDCC4_APPS_CMD_RCGR
280 0x0012300c, // GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR
281 0x00117010, // GCC_QUPV3_WRAP0_S0_CMD_RCGR
282 0x00117140, // GCC_QUPV3_WRAP0_S1_CMD_RCGR
283 0x00117270, // GCC_QUPV3_WRAP0_S2_CMD_RCGR
284 0x001173a0, // GCC_QUPV3_WRAP0_S3_CMD_RCGR
285 0x001174d0, // GCC_QUPV3_WRAP0_S4_CMD_RCGR
286 0x00117600, // GCC_QUPV3_WRAP0_S5_CMD_RCGR
287 0x00117730, // GCC_QUPV3_WRAP0_S6_CMD_RCGR
288 0x00117860, // GCC_QUPV3_WRAP0_S7_CMD_RCGR
289 0x00123144, // GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR
290 0x00118010, // GCC_QUPV3_WRAP1_S0_CMD_RCGR
291 0x00118140, // GCC_QUPV3_WRAP1_S1_CMD_RCGR
292 0x00118270, // GCC_QUPV3_WRAP1_S2_CMD_RCGR
293 0x001183a0, // GCC_QUPV3_WRAP1_S3_CMD_RCGR
294 0x001184d0, // GCC_QUPV3_WRAP1_S4_CMD_RCGR
295 0x00118600, // GCC_QUPV3_WRAP1_S5_CMD_RCGR
296 0x0016b038, // GCC_PCIE_0_AUX_CMD_RCGR
297 0x0018d038, // GCC_PCIE_1_AUX_CMD_RCGR
298 0x0016f014, // GCC_PCIE_PHY_REFGEN_CMD_RCGR
299 0x00175024, // GCC_UFS_CARD_AXI_CMD_RCGR
300 0x0017506c, // GCC_UFS_CARD_ICE_CORE_CMD_RCGR
301 0x00175084, // GCC_UFS_CARD_UNIPRO_CORE_CMD_RCGR
302 0x001750a0, // GCC_UFS_CARD_PHY_AUX_CMD_RCGR
303 0x00177024, // GCC_UFS_PHY_AXI_CMD_RCGR
304 0x0017706c, // GCC_UFS_PHY_ICE_CORE_CMD_RCGR
305 0x00177084, // GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR
306 0x001770a0, // GCC_UFS_PHY_PHY_AUX_CMD_RCGR
307 0x0012327c, // GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR
308 0x0011e010, // GCC_QUPV3_WRAP2_S0_CMD_RCGR
309 0x0011e140, // GCC_QUPV3_WRAP2_S1_CMD_RCGR
310 0x0011e270, // GCC_QUPV3_WRAP2_S2_CMD_RCGR
311 0x0011e3a0, // GCC_QUPV3_WRAP2_S3_CMD_RCGR
312 0x0011e4d0, // GCC_QUPV3_WRAP2_S4_CMD_RCGR
313 0x0011e600, // GCC_QUPV3_WRAP2_S5_CMD_RCGR
314 0x0010d00c, // GCC_RBCPR_MMCX_CMD_RCGR
315 0x00106038, // GCC_PCIE_2_AUX_CMD_RCGR
316};
317
318static const char *const sm8250_rcg_names[] = {
319 "GCC_USB30_PRIM_MASTER_CMD_RCGR",
320 "GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR",
321 "GCC_USB3_PRIM_PHY_AUX_CMD_RCGR",
322 "GCC_USB30_SEC_MASTER_CMD_RCGR",
323 "GCC_USB30_SEC_MOCK_UTMI_CMD_RCGR",
324 "GCC_USB3_SEC_PHY_AUX_CMD_RCGR",
325 "GCC_SDCC2_APPS_CMD_RCGR",
326 "GCC_SDCC4_APPS_CMD_RCGR",
327 "GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR",
328 "GCC_QUPV3_WRAP0_S0_CMD_RCGR",
329 "GCC_QUPV3_WRAP0_S1_CMD_RCGR",
330 "GCC_QUPV3_WRAP0_S2_CMD_RCGR",
331 "GCC_QUPV3_WRAP0_S3_CMD_RCGR",
332 "GCC_QUPV3_WRAP0_S4_CMD_RCGR",
333 "GCC_QUPV3_WRAP0_S5_CMD_RCGR",
334 "GCC_QUPV3_WRAP0_S6_CMD_RCGR",
335 "GCC_QUPV3_WRAP0_S7_CMD_RCGR",
336 "GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR",
337 "GCC_QUPV3_WRAP1_S0_CMD_RCGR",
338 "GCC_QUPV3_WRAP1_S1_CMD_RCGR",
339 "GCC_QUPV3_WRAP1_S2_CMD_RCGR",
340 "GCC_QUPV3_WRAP1_S3_CMD_RCGR",
341 "GCC_QUPV3_WRAP1_S4_CMD_RCGR",
342 "GCC_QUPV3_WRAP1_S5_CMD_RCGR",
343 "GCC_PCIE_0_AUX_CMD_RCGR",
344 "GCC_PCIE_1_AUX_CMD_RCGR",
345 "GCC_PCIE_PHY_REFGEN_CMD_RCGR",
346 "GCC_UFS_CARD_AXI_CMD_RCGR",
347 "GCC_UFS_CARD_ICE_CORE_CMD_RCGR",
348 "GCC_UFS_CARD_UNIPRO_CORE_CMD_RCGR",
349 "GCC_UFS_CARD_PHY_AUX_CMD_RCGR",
350 "GCC_UFS_PHY_AXI_CMD_RCGR",
351 "GCC_UFS_PHY_ICE_CORE_CMD_RCGR",
352 "GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR",
353 "GCC_UFS_PHY_PHY_AUX_CMD_RCGR",
354 "GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR",
355 "GCC_QUPV3_WRAP2_S0_CMD_RCGR",
356 "GCC_QUPV3_WRAP2_S1_CMD_RCGR",
357 "GCC_QUPV3_WRAP2_S2_CMD_RCGR",
358 "GCC_QUPV3_WRAP2_S3_CMD_RCGR",
359 "GCC_QUPV3_WRAP2_S4_CMD_RCGR",
360 "GCC_QUPV3_WRAP2_S5_CMD_RCGR",
361 "GCC_RBCPR_MMCX_CMD_RCGR",
362 "GCC_PCIE_2_AUX_CMD_RCGR",
363};
364
Caleb Connolly78672c62024-04-08 15:06:51 +0200[diff] [blame]365static struct msm_clk_data qcs404_gcc_data = {
366 .resets = sm8250_gcc_resets,
367 .num_resets = ARRAY_SIZE(sm8250_gcc_resets),
368 .clks = sm8250_clks,
369 .num_clks = ARRAY_SIZE(sm8250_clks),
370 .power_domains = sm8250_gdscs,
371 .num_power_domains = ARRAY_SIZE(sm8250_gdscs),
372
373 .enable = sm8250_enable,
374 .set_rate = sm8250_set_rate,
Caleb Connollya17233d2024-08-19 21:34:20 +0200[diff] [blame]375
376 .dbg_pll_addrs = sm8250_gpll_addrs,
377 .num_plls = ARRAY_SIZE(sm8250_gpll_addrs),
378 .dbg_rcg_addrs = sm8250_rcg_addrs,
379 .num_rcgs = ARRAY_SIZE(sm8250_rcg_addrs),
380 .dbg_rcg_names = sm8250_rcg_names,
Caleb Connolly78672c62024-04-08 15:06:51 +0200[diff] [blame]381};
382
383static const struct udevice_id gcc_sm8250_of_match[] = {
384 {
385 .compatible = "qcom,gcc-sm8250",
386 .data = (ulong)&qcs404_gcc_data,
387 },
388 {}
389};
390
391U_BOOT_DRIVER(gcc_sm8250) = {
392 .name = "gcc_sm8250",
393 .id = UCLASS_NOP,
394 .of_match = gcc_sm8250_of_match,
395 .bind = qcom_cc_bind,
396 .flags = DM_FLAG_PRE_RELOC,
397};