Zong Li | feea3fb | 2021-09-01 15:01:39 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (C) 2021 SiFive |
| 4 | */ |
| 5 | |
Zong Li | feea3fb | 2021-09-01 15:01:39 +0800 | [diff] [blame] | 6 | #include <cache.h> |
| 7 | #include <dm.h> |
| 8 | #include <asm/io.h> |
| 9 | #include <dm/device.h> |
| 10 | #include <linux/bitfield.h> |
| 11 | |
| 12 | #define SIFIVE_CCACHE_CONFIG 0x000 |
| 13 | #define SIFIVE_CCACHE_CONFIG_WAYS GENMASK(15, 8) |
| 14 | |
| 15 | #define SIFIVE_CCACHE_WAY_ENABLE 0x008 |
| 16 | |
Nick Hu | 23cfd6f | 2024-10-30 15:58:36 +0800 | [diff] [blame] | 17 | #define SIFIVE_CCACHE_TRUNKCLOCKGATE 0x1000 |
| 18 | #define SIFIVE_CCACHE_TRUNKCLOCKGATE_DISABLE BIT(0) |
| 19 | #define SIFIVE_CCACHE_REGIONCLOCKGATE_DISABLE BIT(1) |
| 20 | |
Zong Li | feea3fb | 2021-09-01 15:01:39 +0800 | [diff] [blame] | 21 | struct sifive_ccache { |
| 22 | void __iomem *base; |
Nick Hu | 23cfd6f | 2024-10-30 15:58:36 +0800 | [diff] [blame] | 23 | bool has_cg; |
| 24 | }; |
| 25 | |
| 26 | struct sifive_ccache_quirks { |
| 27 | bool has_cg; |
Zong Li | feea3fb | 2021-09-01 15:01:39 +0800 | [diff] [blame] | 28 | }; |
| 29 | |
| 30 | static int sifive_ccache_enable(struct udevice *dev) |
| 31 | { |
| 32 | struct sifive_ccache *priv = dev_get_priv(dev); |
| 33 | u32 config; |
| 34 | u32 ways; |
| 35 | |
| 36 | /* Enable all ways of composable cache */ |
| 37 | config = readl(priv->base + SIFIVE_CCACHE_CONFIG); |
| 38 | ways = FIELD_GET(SIFIVE_CCACHE_CONFIG_WAYS, config); |
| 39 | |
| 40 | writel(ways - 1, priv->base + SIFIVE_CCACHE_WAY_ENABLE); |
| 41 | |
Nick Hu | 23cfd6f | 2024-10-30 15:58:36 +0800 | [diff] [blame] | 42 | if (priv->has_cg) { |
| 43 | /* enable clock gating bits */ |
| 44 | config = readl(priv->base + SIFIVE_CCACHE_TRUNKCLOCKGATE); |
| 45 | config &= ~(SIFIVE_CCACHE_TRUNKCLOCKGATE_DISABLE | |
| 46 | SIFIVE_CCACHE_REGIONCLOCKGATE_DISABLE); |
| 47 | writel(config, priv->base + SIFIVE_CCACHE_TRUNKCLOCKGATE); |
| 48 | } |
| 49 | |
Zong Li | feea3fb | 2021-09-01 15:01:39 +0800 | [diff] [blame] | 50 | return 0; |
| 51 | } |
| 52 | |
| 53 | static int sifive_ccache_get_info(struct udevice *dev, struct cache_info *info) |
| 54 | { |
| 55 | struct sifive_ccache *priv = dev_get_priv(dev); |
| 56 | |
Bin Meng | 9f50173 | 2021-09-12 11:15:08 +0800 | [diff] [blame] | 57 | info->base = (uintptr_t)priv->base; |
Zong Li | feea3fb | 2021-09-01 15:01:39 +0800 | [diff] [blame] | 58 | |
| 59 | return 0; |
| 60 | } |
| 61 | |
| 62 | static const struct cache_ops sifive_ccache_ops = { |
| 63 | .enable = sifive_ccache_enable, |
| 64 | .get_info = sifive_ccache_get_info, |
| 65 | }; |
| 66 | |
| 67 | static int sifive_ccache_probe(struct udevice *dev) |
| 68 | { |
| 69 | struct sifive_ccache *priv = dev_get_priv(dev); |
Nick Hu | 23cfd6f | 2024-10-30 15:58:36 +0800 | [diff] [blame] | 70 | const struct sifive_ccache_quirks *quirk = (void *)dev_get_driver_data(dev); |
Zong Li | feea3fb | 2021-09-01 15:01:39 +0800 | [diff] [blame] | 71 | |
Nick Hu | 23cfd6f | 2024-10-30 15:58:36 +0800 | [diff] [blame] | 72 | priv->has_cg = quirk->has_cg; |
Zong Li | feea3fb | 2021-09-01 15:01:39 +0800 | [diff] [blame] | 73 | priv->base = dev_read_addr_ptr(dev); |
| 74 | if (!priv->base) |
| 75 | return -EINVAL; |
| 76 | |
| 77 | return 0; |
| 78 | } |
| 79 | |
Nick Hu | 23cfd6f | 2024-10-30 15:58:36 +0800 | [diff] [blame] | 80 | static const struct sifive_ccache_quirks fu540_ccache = { |
| 81 | .has_cg = false, |
| 82 | }; |
| 83 | |
| 84 | static const struct sifive_ccache_quirks ccache0 = { |
| 85 | .has_cg = true, |
| 86 | }; |
| 87 | |
Zong Li | feea3fb | 2021-09-01 15:01:39 +0800 | [diff] [blame] | 88 | static const struct udevice_id sifive_ccache_ids[] = { |
Nick Hu | 23cfd6f | 2024-10-30 15:58:36 +0800 | [diff] [blame] | 89 | { .compatible = "sifive,fu540-c000-ccache", .data = (ulong)&fu540_ccache }, |
| 90 | { .compatible = "sifive,fu740-c000-ccache", .data = (ulong)&fu540_ccache }, |
| 91 | { .compatible = "sifive,ccache0", .data = (ulong)&ccache0 }, |
Zong Li | feea3fb | 2021-09-01 15:01:39 +0800 | [diff] [blame] | 92 | {} |
| 93 | }; |
| 94 | |
| 95 | U_BOOT_DRIVER(sifive_ccache) = { |
| 96 | .name = "sifive_ccache", |
| 97 | .id = UCLASS_CACHE, |
| 98 | .of_match = sifive_ccache_ids, |
| 99 | .probe = sifive_ccache_probe, |
| 100 | .priv_auto = sizeof(struct sifive_ccache), |
| 101 | .ops = &sifive_ccache_ops, |
| 102 | }; |