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git01.mediatek.com / filogic / uboot / 06a2234f7004de504d5e6883f293259e4e734bfc / . / board / bsh / imx6ulz_smm_m2 / spl.c
blob: 724841b57456029ec227eb4ea142606eb3cde5f6 [file] [log] [blame]
Michael Trimarchi273ab5a2022-09-18 17:09:53 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2
Michael Trimarchi273ab5a2022-09-18 17:09:53 +0200[diff] [blame]3#include <cpu_func.h>
4#include <hang.h>
5#include <init.h>
6#include <asm/arch/clock.h>
7#include <asm/arch/iomux.h>
8#include <asm/arch/imx-regs.h>
9#include <asm/arch/crm_regs.h>
10#include <asm/arch/mx6ull_pins.h>
11#include <asm/arch/mx6-pins.h>
12#include <asm/arch/sys_proto.h>
13#include <asm/gpio.h>
14#include <asm/mach-imx/iomux-v3.h>
15#include <asm/mach-imx/boot_mode.h>
16#include <linux/libfdt.h>
17#include <spl.h>
18#include <asm/arch/mx6-ddr.h>
19
20#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
21 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
22 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
23
24static const iomux_v3_cfg_t uart4_pads[] = {
25 MX6_PAD_UART4_TX_DATA__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
26 MX6_PAD_UART4_RX_DATA__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
27};
28
29static void setup_iomux_uart(void)
30{
31 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
32}
33
34static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
35 .grp_addds = 0x00000028,
36 .grp_ddrmode_ctl = 0x00020000,
37 .grp_b0ds = 0x00000028,
38 .grp_ctlds = 0x00000028,
39 .grp_b1ds = 0x00000028,
40 .grp_ddrpke = 0x00000000,
41 .grp_ddrmode = 0x00020000,
42 .grp_ddr_type = 0x000c0000,
43};
44
45static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
46 .dram_dqm0 = 0x00000028,
47 .dram_dqm1 = 0x00000028,
48 .dram_ras = 0x00000028,
49 .dram_cas = 0x00000028,
50 .dram_odt0 = 0x00000028,
51 .dram_odt1 = 0x00000028,
52 .dram_sdba2 = 0x00000000,
53 .dram_sdclk_0 = 0x00000028,
54 .dram_sdqs0 = 0x00000028,
55 .dram_sdqs1 = 0x00000028,
56 .dram_reset = 0x000c0028,
57};
58
59static struct mx6_mmdc_calibration mx6_mmcd_calib = {
60 .p0_mpwldectrl0 = 0x00000000,
61 .p0_mpwldectrl1 = 0x00100010,
62 .p0_mpdgctrl0 = 0x414c014c,
63 .p0_mpdgctrl1 = 0x00000000,
64 .p0_mprddlctl = 0x40403a42,
65 .p0_mpwrdlctl = 0x4040342e,
66};
67
68static struct mx6_ddr_sysinfo ddr_sysinfo = {
69 .dsize = 0,
70 .cs1_mirror = 0,
71 .cs_density = 32,
72 .ncs = 1,
73 .bi_on = 1,
74 .rtt_nom = 1,
75 .rtt_wr = 0,
76 .ralat = 5,
77 .walat = 1,
78 .mif3_mode = 3,
79 .rst_to_cke = 0x23, /* 33 cycles (JEDEC value for DDR3) - total of 500 us */
80 .sde_to_rst = 0x10, /* 14 cycles (JEDEC value for DDR3) - total of 200 us */
81 .refsel = 1,
82 .refr = 3,
83};
84
85static struct mx6_ddr3_cfg mem_ddr = {
86 .mem_speed = 1333,
87 .density = 2,
88 .width = 16,
89 .banks = 8,
90 .rowaddr = 13,
91 .coladdr = 10,
92 .pagesz = 2,
93 .trcd = 1350,
94 .trcmin = 4950,
95 .trasmin = 3600,
96};
97
98static void ccgr_init(void)
99{
100 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
101
102 writel(0xFFFFFFFF, &ccm->CCGR0);
103 writel(0xFFFFFFFF, &ccm->CCGR1);
104 writel(0xFFFFFFFF, &ccm->CCGR2);
105 writel(0xFFFFFFFF, &ccm->CCGR3);
106 writel(0xFFFFFFFF, &ccm->CCGR4);
107 writel(0xFFFFFFFF, &ccm->CCGR5);
108 writel(0xFFFFFFFF, &ccm->CCGR6);
109}
110
111static void imx6ul_spl_dram_cfg(void)
112{
113 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
114 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
115}
116
117void board_init_f(ulong dummy)
118{
119 ccgr_init();
120 arch_cpu_init();
121 timer_init();
122 setup_iomux_uart();
123 preloader_console_init();
124 imx6ul_spl_dram_cfg();
125}
126
127void reset_cpu(void)
128{
129}