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git01.mediatek.com / filogic / uboot / 068b2add06c1f1039e2a4b372aaaf7d9e63947a3 / . / board / keymile / common / common.h
blob: aab706e6c9c0457a28c360428aa046040ca52c79 [file] [log] [blame]
Heiko Schocherd19a6ec2008-11-21 08:29:40 +0100[diff] [blame]1/*
2 * (C) Copyright 2008
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 */
10
11#ifndef __KEYMILE_COMMON_H
12#define __KEYMILE_COMMON_H
13
Heiko Schocher8ce3dd52011-03-15 16:52:29 +0100[diff] [blame]14#define WRG_RESET 0x80
15#define H_OPORTS_14 0x40
16#define WRG_LED 0x02
17#define WRL_BOOT 0x01
18
Stefan Biglerabcd23c2012-05-04 10:55:55 +0200[diff] [blame]19#define OPRTL_XBUFENA 0x20
20
Heiko Schocher8ce3dd52011-03-15 16:52:29 +0100[diff] [blame]21#define H_OPORTS_SCC4_ENA 0x10
22#define H_OPORTS_SCC4_FD_ENA 0x04
23#define H_OPORTS_FCC1_PW_DWN 0x01
24
25#define PIGGY_PRESENT 0x80
26
27struct km_bec_fpga {
28 unsigned char id;
29 unsigned char rev;
30 unsigned char oprth;
31 unsigned char oprtl;
32 unsigned char res1[3];
33 unsigned char bprth;
34 unsigned char bprtl;
Thomas Herzmann94fbf522012-05-04 10:55:56 +0200[diff] [blame]35 unsigned char gprt3;
36 unsigned char gprt2;
37 unsigned char gprt1;
38 unsigned char gprt0;
39 unsigned char res2[2];
Heiko Schocher8ce3dd52011-03-15 16:52:29 +0100[diff] [blame]40 unsigned char prst;
41 unsigned char res3[0xfff0];
42 unsigned char pgy_id;
43 unsigned char pgy_rev;
44 unsigned char pgy_outputs;
45 unsigned char pgy_eth;
46};
47
Huber, Andreas49adfa82011-05-02 22:56:54 +0000[diff] [blame]48#define BFTICU_DIPSWITCH_MASK 0x0f
49
50/*
51 * BFTICU FPGA iomap
52 * BFTICU is used on mgcoge and mgocge3ne
53 */
54struct bfticu_iomap {
55 u8 xi_ena; /* General defect enable */
56 u8 pack1[3];
57 u8 en_csn;
58 u8 pack2;
59 u8 safe_mem;
60 u8 pack3;
61 u8 id;
62 u8 pack4;
63 u8 rev;
64 u8 build;
65 u8 p_frc;
66 u8 p_msk;
67 u8 pack5[2];
68 u8 xg_int;
69 u8 pack6[15];
70 u8 s_conf;
71 u8 pack7;
72 u8 dmx_conf12;
73 u8 pack8;
74 u8 s_clkslv;
75 u8 pack9[11];
76 u8 d_conf;
77 u8 d_mask_ca;
78 u8 d_pll_del;
79 u8 pack10[16];
80 u8 t_conf_ca;
81 u8 t_mask_ca;
82 u8 pack11[13];
83 u8 m_def0;
84 u8 m_def1;
85 u8 m_def2;
86 u8 m_def3;
87 u8 m_def4;
88 u8 m_def5;
89 u8 m_def_trap0;
90 u8 m_def_trap1;
91 u8 m_def_trap2;
92 u8 m_def_trap3;
93 u8 m_def_trap4;
94 u8 m_def_trap5;
95 u8 m_mask_def0;
96 u8 m_mask_def1;
97 u8 m_mask_def2;
98 u8 m_mask_def3;
99 u8 m_mask_def4;
100 u8 m_mask_def5;
101 u8 m_def_mask0;
102 u8 m_def_mask1;
103 u8 m_def_mask2;
104 u8 m_def_mask3;
105 u8 m_def_mask4;
106 u8 m_def_mask5;
107 u8 m_def_pri;
108 u8 pack12[11];
109 u8 hw_status;
110 u8 pack13;
111 u8 hw_control1;
112 u8 hw_control2;
113 u8 hw_control3;
114 u8 pack14[7];
115 u8 led_on; /* Leds */
116 u8 pack15;
117 u8 sfp_control; /* SFP modules */
118 u8 pack16;
119 u8 alarm_control; /* Alarm output */
120 u8 pack17;
121 u8 icps; /* ICN clock pulse shaping */
122 u8 mswitch; /* Read mode switch */
123 u8 pack18[6];
124 u8 pb_dbug;
125};
126
Heiko Schocherb7aa50f2011-01-06 10:25:26 +0100[diff] [blame]127#if !defined(CONFIG_PIGGY_MAC_ADRESS_OFFSET)
128#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 0
129#endif
130
Heiko Schocher8ce3dd52011-03-15 16:52:29 +0100[diff] [blame]131int ethernet_present(void);
132int ivm_read_eeprom(void);
Heiko Schocherd19a6ec2008-11-21 08:29:40 +0100[diff] [blame]133
Valentin Longchamp6633fed2012-07-05 05:05:05 +0000[diff] [blame]134int trigger_fpga_config(void);
135int wait_for_fpga_config(void);
136int fpga_reset(void);
137int toggle_eeprom_spi_bus(void);
138
Heiko Schochercfc58042010-04-26 13:07:28 +0200[diff] [blame]139int set_km_env(void);
Heiko Schocher8ce3dd52011-03-15 16:52:29 +0100[diff] [blame]140int fdt_set_node_and_value(void *blob,
Heiko Schocher875f47282009-07-09 12:04:18 +0200[diff] [blame]141 char *nodename,
142 char *regname,
143 void *var,
144 int size);
Heiko Schocher8ce3dd52011-03-15 16:52:29 +0100[diff] [blame]145int fdt_get_node_and_value(void *blob,
Heiko Schocher875f47282009-07-09 12:04:18 +0200[diff] [blame]146 char *nodename,
147 char *propname,
148 void **var);
Heiko Schocher8ce3dd52011-03-15 16:52:29 +0100[diff] [blame]149
Holger Brunck015a60f2011-09-14 10:54:12 +0200[diff] [blame]150#define DELAY_ABORT_SEQ 62 /* @200kHz 9 clocks = 44us, 62us is ok */
151#define DELAY_HALF_PERIOD (500 / (CONFIG_SYS_I2C_SPEED / 1000))
152
Heiko Schocher8ce3dd52011-03-15 16:52:29 +0100[diff] [blame]153int i2c_soft_read_pin(void);
Holger Brunckbf20a882011-06-05 22:22:18 +0000[diff] [blame]154int i2c_make_abort(void);
Heiko Schocherd19a6ec2008-11-21 08:29:40 +0100[diff] [blame]155#endif /* __KEYMILE_COMMON_H */