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Matthias Fuchs1df4d252009-07-22 13:56:21 +02001/*
2 * (C) Copyright 2009
3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu
4 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Matthias Fuchs1df4d252009-07-22 13:56:21 +02006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11#define CONFIG_405EP 1 /* This is a PPC405 CPU */
Matthias Fuchs1df4d252009-07-22 13:56:21 +020012#define CONFIG_PMC405DE 1 /* ...on a PMC405DE board */
13
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020014#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
Matthias Fuchs7a9021b2015-01-12 22:47:34 +010015#define CONFIG_DISPLAY_BOARDINFO
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020016
Matthias Fuchs1df4d252009-07-22 13:56:21 +020017#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
18#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
19#define CONFIG_BOARD_TYPES 1 /* support board types */
20
21#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
22
23#define CONFIG_BAUDRATE 115200
24#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
25
26#undef CONFIG_BOOTARGS
27#undef CONFIG_BOOTCOMMAND
28
29#define CONFIG_PREBOOT /* enable preboot variable */
30
31#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change*/
32
Matthias Fuchs1df4d252009-07-22 13:56:21 +020033#define CONFIG_HAS_ETH1
34
35#define CONFIG_PPC4xx_EMAC
36#define CONFIG_MII 1 /* MII PHY management */
37#define CONFIG_PHY_ADDR 1 /* PHY address */
38#define CONFIG_PHY1_ADDR 2 /* 2nd PHY address */
39
40#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
41
42/*
43 * BOOTP options
44 */
45#define CONFIG_BOOTP_SUBNETMASK
46#define CONFIG_BOOTP_GATEWAY
47#define CONFIG_BOOTP_HOSTNAME
48#define CONFIG_BOOTP_BOOTPATH
49#define CONFIG_BOOTP_DNS
50#define CONFIG_BOOTP_DNS2
51#define CONFIG_BOOTP_SEND_HOSTNAME
52
53/*
54 * Command line configuration.
55 */
Matthias Fuchs1df4d252009-07-22 13:56:21 +020056#define CONFIG_CMD_BSP
57#define CONFIG_CMD_CHIP_CONFIG
58#define CONFIG_CMD_DATE
Matthias Fuchs1df4d252009-07-22 13:56:21 +020059#define CONFIG_CMD_EEPROM
Matthias Fuchs1df4d252009-07-22 13:56:21 +020060#define CONFIG_CMD_IRQ
61#define CONFIG_CMD_MII
Matthias Fuchs1df4d252009-07-22 13:56:21 +020062#define CONFIG_CMD_PCI
Matthias Fuchs1df4d252009-07-22 13:56:21 +020063
Matthias Fuchs1df4d252009-07-22 13:56:21 +020064#undef CONFIG_WATCHDOG /* watchdog disabled */
65#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
66#define CONFIG_PRAM 0
67
68/*
69 * Miscellaneous configurable options
70 */
71#define CONFIG_SYS_LONGHELP
Matthias Fuchs1df4d252009-07-22 13:56:21 +020072
73#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
74#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
75#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
76#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
77
78#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
79#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console info */
80
81#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
82#define CONFIG_SYS_MEMTEST_END 0x3000000 /* 1 ... 48 MB in DRAM */
83
Stefan Roese3ddce572010-09-20 16:05:31 +020084#define CONFIG_CONS_INDEX 2 /* Use UART1 */
Stefan Roese3ddce572010-09-20 16:05:31 +020085#define CONFIG_SYS_NS16550_SERIAL
86#define CONFIG_SYS_NS16550_REG_SIZE 1
87#define CONFIG_SYS_NS16550_CLK get_serial_clock()
88
Matthias Fuchs1df4d252009-07-22 13:56:21 +020089#undef CONFIG_SYS_EXT_SERIAL_CLOCK
90#define CONFIG_SYS_BASE_BAUD 691200
Matthias Fuchs1df4d252009-07-22 13:56:21 +020091
Matthias Fuchs1df4d252009-07-22 13:56:21 +020092#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
93#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
94
Matthias Fuchs1df4d252009-07-22 13:56:21 +020095#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Matthias Fuchs1df4d252009-07-22 13:56:21 +020096#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
97#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
98#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
99
Matthias Fuchs1df4d252009-07-22 13:56:21 +0200100/*
101 * PCI stuff
102 */
103#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
104#define PCI_HOST_FORCE 1 /* configure as pci host */
105#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
106
107#define CONFIG_PCI /* include pci support */
Gabor Juhosb4458732013-05-30 07:06:12 +0000108#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Matthias Fuchs1df4d252009-07-22 13:56:21 +0200109#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
110#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
111
112#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
113
114/*
115 * PCI identification
116 */
117#define CONFIG_SYS_PCI_SUBSYS_VENDORID PCI_VENDOR_ID_ESDGMBH
118#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x040e /* Dev ID: Non-Monarch */
119#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x040f /* Dev ID: Monarch */
120#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC
121#define CONFIG_SYS_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST
122
123#define CONFIG_SYS_PCI_CLASSCODE CONFIG_SYS_PCI_CLASSCODE_MONARCH
124#define CONFIG_SYS_PCI_SUBSYS_DEVICEID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
125
126#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
127#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable=1 */
128#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
129#define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to CPLD, GPIO */
130#define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable=1 */
131#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
132
Matthias Fuchsa9d47992009-09-07 17:00:41 +0200133#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */
134
Matthias Fuchs1df4d252009-07-22 13:56:21 +0200135/*
136 * For booting Linux, the board info and command line data
137 * have to be in the first 8 MB of memory, since this is
138 * the maximum mapped by the Linux kernel during initialization.
139 */
140#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
141/*
142 * FLASH organization
143 */
144#define CONFIG_SYS_FLASH_CFI 1 /* CFI compatible */
145#define CONFIG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */
146
147#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
148
149#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max. no. memory banks */
150#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per chip */
151
152#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* erase timeout (in ms) */
153#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* write timeout (in ms) */
154
155#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* buffered writes (faster) */
156#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */
157
158#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* 'E' for empty sector (flinfo) */
159#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
160
Matthias Fuchs1df4d252009-07-22 13:56:21 +0200161/*
162 * Start addresses for the final memory configuration
163 * (Set up by the startup code)
164 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
165 */
166#define CONFIG_SYS_SDRAM_BASE 0x00000000
167#define CONFIG_SYS_FLASH_BASE 0xfe000000
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200168#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
169#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
Matthias Fuchs1df4d252009-07-22 13:56:21 +0200170#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
171
172/*
173 * Environment in EEPROM setup
174 */
175#define CONFIG_ENV_IS_IN_EEPROM 1
176#define CONFIG_ENV_OFFSET 0x100
177#define CONFIG_ENV_SIZE 0x700
178
179/*
180 * I2C EEPROM (24W16) for environment
181 */
Dirk Eibach42b204f2013-04-25 02:40:01 +0000182#define CONFIG_SYS_I2C
183#define CONFIG_SYS_I2C_PPC4XX
184#define CONFIG_SYS_I2C_PPC4XX_CH0
185#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
186#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
Matthias Fuchs1df4d252009-07-22 13:56:21 +0200187
188#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24W16 */
189#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
190/* mask of address bits that overflow into the "EEPROM chip address" */
191#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
192#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
193 /* 16 byte page write mode using*/
194 /* last 4 bits of the address */
195#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
196#define CONFIG_SYS_EEPROM_WREN 1
197
198#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50
199#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0x40
200#define CONFIG_4xx_CONFIG_BLOCKSIZE 0x20
201
202/*
203 * RTC
204 */
205#define CONFIG_RTC_RX8025
206
207/*
208 * External Bus Controller (EBC) Setup
209 * (max. 55MHZ EBC clock)
210 */
211/* Memory Bank 0 (NOR flash) BAS=0xFE0,BS=32MB,BU=R/W,BW=16bit */
212#define CONFIG_SYS_EBC_PB0AP 0x03017200
213#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xba000)
214
215/* Memory Bank 1 (CPLD) BAS=0xEF0,BS=16MB,BU=R/W,BW=16bit */
216#define CONFIG_SYS_CPLD_BASE 0xef000000
217#define CONFIG_SYS_EBC_PB1AP 0x00800000
218#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_CPLD_BASE | 0x18000)
219
220/*
221 * Definitions for initial stack pointer and data area (in data cache)
222 */
223/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
224#define CONFIG_SYS_TEMP_STACK_OCM 1
225
226/* On Chip Memory location */
227#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
228#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
229/* inside SDRAM */
230#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
231/* End of used area in RAM */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200232#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
Matthias Fuchs1df4d252009-07-22 13:56:21 +0200233
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200234#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
Wolfgang Denk0191e472010-10-26 14:34:52 +0200235 GENERATED_GBL_DATA_SIZE)
Matthias Fuchs1df4d252009-07-22 13:56:21 +0200236#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
237
238/*
239 * GPIO Configuration
240 */
241#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alt1 */ \
242{ \
243/* GPIO Core 0 */ \
244{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
245{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
246{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
247{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
248{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
249{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
250{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO6 TS4 */ \
251{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \
252{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
253{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO9 TrcClk */ \
254{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
255{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
256{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
257{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
258{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
259{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
260{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
261{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
262{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
263{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
264{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
265{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
266{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
267{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
268{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
269{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
270{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
271{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
272{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
273{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
274{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
275{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
276} \
277}
278
279#define CONFIG_SYS_GPIO_HWREV_MASK (0xf0000000 >> 1) /* GPIO1..4 */
280#define CONFIG_SYS_GPIO_HWREV_SHIFT 27
281#define CONFIG_SYS_GPIO_LEDRUN_N (0x80000000 >> 5) /* GPIO5 */
282#define CONFIG_SYS_GPIO_LEDA_N (0x80000000 >> 6) /* GPIO6 */
283#define CONFIG_SYS_GPIO_LEDB_N (0x80000000 >> 7) /* GPIO7 */
284#define CONFIG_SYS_GPIO_SELFRST_N (0x80000000 >> 8) /* GPIO8 */
285#define CONFIG_SYS_GPIO_EEPROM_WP (0x80000000 >> 9) /* GPIO9 */
286#define CONFIG_SYS_GPIO_MONARCH_N (0x80000000 >> 11) /* GPIO11 */
287#define CONFIG_SYS_GPIO_EREADY (0x80000000 >> 12) /* GPIO12 */
288#define CONFIG_SYS_GPIO_M66EN (0x80000000 >> 13) /* GPIO13 */
289
290/*
291 * Default speed selection (cpu_plb_opb_ebc) in mhz.
292 * This value will be set if iic boot eprom is disabled.
293 */
294#undef CONFIG_SYS_FCPU333MHZ
295#define CONFIG_SYS_FCPU266MHZ
296#undef CONFIG_SYS_FCPU133MHZ
297
298#if defined(CONFIG_SYS_FCPU333MHZ)
299/*
300 * CPU: 333MHz
301 * PLB/SDRAM/MAL: 111MHz
302 * OPB: 55MHz
303 * EBC: 55MHz
304 * PCI: 55MHz (111MHz on M66EN=1)
305 */
306#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
307 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
308 PLL_MALDIV_1 | PLL_PCIDIV_2)
309#define PLLMR1_DEFAULT (PLL_FBKDIV_10 | \
310 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
311 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
312#endif
313
314#if defined(CONFIG_SYS_FCPU266MHZ)
315/*
316 * CPU: 266MHz
317 * PLB/SDRAM/MAL: 133MHz
318 * OPB: 66MHz
319 * EBC: 44MHz
320 * PCI: 44MHz (66MHz on M66EN=1)
321 */
322#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
323 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
324 PLL_MALDIV_1 | PLL_PCIDIV_3)
325#define PLLMR1_DEFAULT (PLL_FBKDIV_8 | \
326 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
327 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
328#endif
329
330#if defined(CONFIG_SYS_FCPU133MHZ)
331/*
332 * CPU: 133MHz
333 * PLB/SDRAM/MAL: 133MHz
334 * OPB: 66MHz
335 * EBC: 44MHz
336 * PCI: 44MHz (66MHz on M66EN=1)
337 */
338#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
339 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
340 PLL_MALDIV_1 | PLL_PCIDIV_3)
341#define PLLMR1_DEFAULT (PLL_FBKDIV_4 | \
342 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
343 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
344#endif
345
346#endif /* __CONFIG_H */