| Stefan Roese | 5ff4c3f | 2005-08-15 12:31:23 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2005 |
| 3 | * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com |
| Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| Stefan Roese | 5ff4c3f | 2005-08-15 12:31:23 +0200 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <ppc_asm.tmpl> |
| Stefan Roese | 94b6270 | 2010-04-14 13:57:18 +0200 | [diff] [blame] | 8 | #include <asm/mmu.h> |
| Stefan Roese | 5ff4c3f | 2005-08-15 12:31:23 +0200 | [diff] [blame] | 9 | #include <config.h> |
| Stefan Roese | 3ddce57 | 2010-09-20 16:05:31 +0200 | [diff] [blame] | 10 | #include <asm/ppc4xx.h> |
| Stefan Roese | 5ff4c3f | 2005-08-15 12:31:23 +0200 | [diff] [blame] | 11 | |
| Stefan Roese | 5ff4c3f | 2005-08-15 12:31:23 +0200 | [diff] [blame] | 12 | /************************************************************************** |
| 13 | * TLB TABLE |
| 14 | * |
| 15 | * This table is used by the cpu boot code to setup the initial tlb |
| 16 | * entries. Rather than make broad assumptions in the cpu source tree, |
| 17 | * this table lets each board set things up however they like. |
| 18 | * |
| 19 | * Pointer to the table is returned in r1 |
| 20 | * |
| 21 | *************************************************************************/ |
| 22 | |
| 23 | .section .bootpg,"ax" |
| 24 | .globl tlbtab |
| 25 | |
| 26 | tlbtab: |
| 27 | tlbtab_start |
| Stefan Roese | 94b6270 | 2010-04-14 13:57:18 +0200 | [diff] [blame] | 28 | tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG) |
| 29 | tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG) |
| 30 | tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG) |
| 31 | tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG ) |
| 32 | tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG ) |
| 33 | tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_RWX | SA_IG ) |
| 34 | tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_RWX | SA_IG ) |
| 35 | tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG ) |
| 36 | tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG ) |
| Stefan Roese | 5ff4c3f | 2005-08-15 12:31:23 +0200 | [diff] [blame] | 37 | tlbtab_end |