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git01.mediatek.com / filogic / uboot / 065fd4a88225a10532bef6922a1a946284fd67f4 / . / board / matrix_vision / mergerbox / pci.c
blob: 480f3ed387f0567a3b010a583a50e29cc33a0ae0 [file] [log] [blame]
Andre Schwarzc82fdea2011-04-14 15:11:44 +0200[diff] [blame]1/*
2 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
3 *
4 * Copyright (C) 2011 Matrix Vision GmbH
5 * Andre Schwarz <andre.schwarz@matrix-vision.de>
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]7 * SPDX-License-Identifier: GPL-2.0+
Andre Schwarzc82fdea2011-04-14 15:11:44 +0200[diff] [blame]8 */
9
10#include <common.h>
11#include <mpc83xx.h>
12#include <pci.h>
13#include <asm/io.h>
14#include <asm/fsl_mpc83xx_serdes.h>
15#include "mergerbox.h"
16#include "fpga.h"
17#include "../common/mv_common.h"
18
19static struct pci_region pci_regions[] = {
20 {
21 .bus_start = CONFIG_SYS_PCI_MEM_BASE,
22 .phys_start = CONFIG_SYS_PCI_MEM_PHYS,
23 .size = CONFIG_SYS_PCI_MEM_SIZE,
24 .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH
25 },
26 {
27 .bus_start = CONFIG_SYS_PCI_MMIO_BASE,
28 .phys_start = CONFIG_SYS_PCI_MMIO_PHYS,
29 .size = CONFIG_SYS_PCI_MMIO_SIZE,
30 .flags = PCI_REGION_MEM
31 },
32 {
33 .bus_start = CONFIG_SYS_PCI_IO_BASE,
34 .phys_start = CONFIG_SYS_PCI_IO_PHYS,
35 .size = CONFIG_SYS_PCI_IO_SIZE,
36 .flags = PCI_REGION_IO
37 }
38};
39
40static struct pci_region pcie_regions_0[] = {
41 {
42 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
43 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
44 .size = CONFIG_SYS_PCIE1_MEM_SIZE,
45 .flags = PCI_REGION_MEM,
46 },
47 {
48 .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
49 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
50 .size = CONFIG_SYS_PCIE1_IO_SIZE,
51 .flags = PCI_REGION_IO,
52 },
53};
54
55static struct pci_region pcie_regions_1[] = {
56 {
57 .bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
58 .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
59 .size = CONFIG_SYS_PCIE2_MEM_SIZE,
60 .flags = PCI_REGION_MEM,
61 },
62 {
63 .bus_start = CONFIG_SYS_PCIE2_IO_BASE,
64 .phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
65 .size = CONFIG_SYS_PCIE2_IO_SIZE,
66 .flags = PCI_REGION_IO,
67 },
68};
69
70void pci_init_board(void)
71{
72 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
73 volatile sysconf83xx_t *sysconf = &immr->sysconf;
74 volatile clk83xx_t *clk = (clk83xx_t *)&immr->clk;
75 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
76 volatile law83xx_t *pcie_law = sysconf->pcielaw;
77 struct pci_region *reg[] = { pci_regions };
78 struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
79
80 volatile gpio83xx_t *gpio;
81 gpio = (gpio83xx_t *)&immr->gpio[0];
82
83 gpio->dat = MV_GPIO1_DAT;
84 gpio->odr = MV_GPIO1_ODE;
85 gpio->dir = MV_GPIO1_OUT;
86
87 gpio = (gpio83xx_t *)&immr->gpio[1];
88
89 gpio->dat = MV_GPIO2_DAT;
90 gpio->odr = MV_GPIO2_ODE;
91 gpio->dir = MV_GPIO2_OUT;
92
93 printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh,
94 immr->sysconf.sicrl);
95
96 /* Enable PCI_CLK[0:1] */
97 clk->occr |= 0xc0000000;
98 udelay(2000);
99
100 mergerbox_init_fpga();
101 mv_load_fpga();
102
103 mergerbox_tft_dim(0);
104
105 /* Configure PCI Local Access Windows */
106 pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
107 pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
108
109 pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
110 pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
111
112 udelay(2000);
113
114 mpc83xx_pci_init(1, reg);
115
116 /* Deassert the resets in the control register */
117 out_be32(&sysconf->pecr1, 0xE0008000);
118 out_be32(&sysconf->pecr2, 0xE0008000);
119 udelay(2000);
120
121 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
122 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
123
124 out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
125 out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
126
127 mpc83xx_pcie_init(2, pcie_reg);
128}